Understanding the Cortex-M4 Timestamp Generator and PSELCTRL Region
The Cortex-M4 processor, a member of the ARM Cortex-M family, is widely used in embedded systems for its balance of performance and power efficiency. One of its features is the Timestamp Generator (TSGEN), which provides a high-resolution timestamp for debugging and profiling purposes. The TSGEN is controlled via the Counter Control Register (CNTCR), located in the PSELCTRL region of the CoreSight system. However, the PSELCTRL region’s base address is not fixed and must be determined by scanning the ROM table, which lists the memory-mapped addresses of all CoreSight components.
The PSELCTRL region is part of the CoreSight architecture, which is a standardized debug and trace infrastructure for ARM processors. CoreSight components, including the TSGEN, are identified by Peripheral Identification (PID) and Component Identification (CID) registers. These identifiers are used to map the components to their respective memory addresses. The ROM table, typically located at 0xE00FF000, contains entries that point to the base addresses of these components. Each entry in the ROM table includes a PID and CID, which must be cross-referenced with the CoreSight Technical Reference Manual to identify the corresponding component.
The challenge lies in locating the PSELCTRL region and enabling the TSGEN. This requires a deep understanding of the CoreSight architecture, the ROM table structure, and the specific implementation of the Cortex-M4 processor in the target system. For example, the STM32L433CC microcontroller, based on the Cortex-M4, does not include the TSGEN, as indicated by its datasheet. This highlights the importance of verifying the presence of specific CoreSight components in the target hardware before attempting to configure them.
Missing or Misconfigured ROM Table Entries for CoreSight Components
One of the primary issues when working with the Cortex-M4’s CoreSight components is the absence or misconfiguration of entries in the ROM table. The ROM table is a critical resource for locating CoreSight components, as it provides the base addresses for each component. If the ROM table is incomplete or incorrectly configured, it becomes impossible to locate the PSELCTRL region and, consequently, the CNTCR register for the TSGEN.
The ROM table is typically located at 0xE00FF000, but this address can vary depending on the specific implementation of the Cortex-M4 processor. Each entry in the ROM table contains a PID and CID, which must match the values specified in the CoreSight Technical Reference Manual. For example, the PID for the PSELCTRL region is 0x4, as mentioned in the manual. If the ROM table does not contain an entry with this PID, the PSELCTRL region is either not implemented or located at a different address.
In some cases, the ROM table may contain entries for other CoreSight components, such as the Data Watchpoint and Trace (DWT) unit or the Instrumentation Trace Macrocell (ITM), but not for the PSELCTRL region. This can occur if the TSGEN is not implemented in the target hardware, as is the case with the STM32L433CC microcontroller. To verify the presence of the TSGEN, developers must scan the ROM table and compare the PIDs and CIDs against the values specified in the CoreSight manual.
Another potential issue is the misinterpretation of the ROM table entries. Each entry in the ROM table includes a base address offset, which must be added to the ROM table’s base address to obtain the actual memory-mapped address of the component. For example, if the ROM table is located at 0xE00FF000 and an entry has an offset of 0x1000, the component’s base address is 0xE00FF000 + 0x1000 = 0xE0100000. Misinterpreting these offsets can lead to incorrect addresses and failed attempts to access the PSELCTRL region.
Scanning the ROM Table and Enabling the Timestamp Generator
To locate and enable the TSGEN on a Cortex-M4 processor, developers must follow a systematic approach to scan the ROM table, identify the PSELCTRL region, and configure the CNTCR register. This process involves reading the ROM table entries, comparing the PIDs and CIDs against the CoreSight manual, and calculating the base addresses of the CoreSight components.
The first step is to read the ROM table located at 0xE00FF000. Each entry in the ROM table is 32 bits wide and contains a base address offset and a set of flags. The least significant bit (LSB) of each entry indicates whether the entry is valid. If the LSB is 0, the entry is not present. Developers must scan the ROM table and identify valid entries by checking the LSB of each entry.
Once valid entries are identified, the next step is to read the PID and CID registers for each entry. These registers are located at offsets 0xFE0 and 0xFF0, respectively, from the base address of each component. The PID and CID values must match those specified in the CoreSight Technical Reference Manual. For example, the PID for the PSELCTRL region is 0x4, and the CID is 0xB105100D. If a match is found, the base address of the PSELCTRL region can be calculated by adding the offset from the ROM table entry to the ROM table’s base address.
After locating the PSELCTRL region, developers can access the CNTCR register to enable the TSGEN. The CNTCR register is located at an offset of 0x00 from the base address of the PSELCTRL region. Writing a value of 0x1 to the CNTCR register enables the TSGEN, while writing 0x0 disables it. It is important to note that the TSGEN must be enabled before it can be used for timestamp generation.
In cases where the TSGEN is not implemented, such as in the STM32L433CC microcontroller, developers must rely on alternative methods for timestamp generation. This may involve using other CoreSight components, such as the DWT unit, or implementing a software-based timestamp generator. However, these alternatives may not provide the same level of precision and performance as the TSGEN.
Below is a summary of the steps involved in locating and enabling the TSGEN:
- Read the ROM Table: Start by reading the ROM table located at 0xE00FF000. Identify valid entries by checking the LSB of each entry.
- Read PID and CID Registers: For each valid entry, read the PID and CID registers located at offsets 0xFE0 and 0xFF0, respectively.
- Compare PID and CID Values: Compare the PID and CID values against those specified in the CoreSight Technical Reference Manual. Look for a match with the PSELCTRL region (PID = 0x4, CID = 0xB105100D).
- Calculate Base Address: If a match is found, calculate the base address of the PSELCTRL region by adding the offset from the ROM table entry to the ROM table’s base address.
- Enable TSGEN: Access the CNTCR register at an offset of 0x00 from the base address of the PSELCTRL region. Write a value of 0x1 to enable the TSGEN.
By following these steps, developers can successfully locate and enable the TSGEN on Cortex-M4 processors that implement this feature. However, it is crucial to verify the presence of the TSGEN in the target hardware before attempting to configure it, as not all Cortex-M4 implementations include this component.
Example: Scanning the ROM Table on an STM32L552 Microcontroller
To illustrate the process of scanning the ROM table and identifying CoreSight components, consider the example of an STM32L552 microcontroller, which is based on the Cortex-M33 processor. The ROM table for this microcontroller is located at 0xE00FE000, and the following entries are read:
| ROM Table Entry | Base Address Offset | CID | PID | Component |
|---|---|---|---|---|
| ROMTbl[0][0] | 0xE00FF000 | 0xB105100D | 0x000BB4C9 | ROM Table |
| ROMTbl[1][0] | 0xE000E000 | 0xB105900D | 0x000BBD21 | Cortex-M33 |
| ROMTbl[1][1] | 0xE0001000 | 0xB105900D | 0x000BBD21 | DWT |
| ROMTbl[1][2] | 0xE0002000 | 0xB105900D | 0x000BBD21 | FPB |
| ROMTbl[1][3] | 0xE0000000 | 0xB105900D | 0x000BBD21 | ITM |
| ROMTbl[1][5] | 0xE0041000 | 0xB105900D | 0x002BBD21 | ETM |
| ROMTbl[1][6] | 0xE0042000 | 0xB105900D | 0x000BBD21 | CTI |
| ROMTbl[0][1] | 0xE0040000 | 0xB105900D | 0x000BBD21 | Cortex-M33 |
In this example, the ROM table contains entries for various CoreSight components, including the DWT, FPB, ITM, ETM, and CTI. However, there is no entry for the PSELCTRL region, indicating that the TSGEN is not implemented in this microcontroller. This highlights the importance of verifying the presence of specific CoreSight components in the target hardware before attempting to configure them.
Conclusion
Locating and enabling the Timestamp Generator on a Cortex-M4 processor requires a thorough understanding of the CoreSight architecture, the ROM table structure, and the specific implementation of the processor in the target hardware. By systematically scanning the ROM table, identifying valid entries, and comparing PID and CID values, developers can determine the presence and location of the PSELCTRL region. Once the PSELCTRL region is located, the CNTCR register can be accessed to enable the TSGEN. However, it is crucial to verify the presence of the TSGEN in the target hardware, as not all Cortex-M4 implementations include this component. In cases where the TSGEN is not available, alternative methods for timestamp generation must be employed.
