APB Single Master to Multiple Slaves Communication and Slave Selection Mechanism

APB Slave Selection Mechanism and Address Decoding in Single-Master Systems

In an Advanced Peripheral Bus (APB) system with a single master and multiple slaves, the master communicates with one slave at a time. The selection of the slave is determined by the PSEL (Peripheral Select) signal, which is generated based on address decoding. The PSEL signal is a single-bit signal per slave, meaning each slave has its own dedicated PSEL line. When the master initiates a transaction, the address of the transaction is decoded to determine which slave is being targeted. The PSEL signal corresponding to the targeted slave is asserted (set high), while all other PSEL signals remain low.

The address decoding process is typically handled by an interconnect or a decoder logic block. The master provides the address (PADDR) as part of the transaction, and the interconnect decodes this address to determine which slave is being accessed. For example, if the system has four slaves, the address space might be divided into four contiguous regions, with each region assigned to a specific slave. If the address falls within the range assigned to Slave 1, the PSEL1 signal is asserted. Similarly, if the address falls within the range assigned to Slave 2, the PSEL2 signal is asserted, and so on.

It is important to note that the PSEL signal is not encoded as a bus (e.g., PSEL[1:0] for four slaves). Instead, each slave has its own dedicated PSEL line. This design simplifies the slave’s logic, as each slave only needs to monitor its own PSEL signal and does not need to decode a multi-bit PSEL bus. The interconnect or decoder logic is responsible for ensuring that only one PSEL signal is high at any given time, as the APB protocol does not support simultaneous transactions with multiple slaves.

The address decoding process is typically implemented using a simple combinational logic circuit that compares the address (PADDR) with predefined address ranges for each slave. For example, if Slave 1 is assigned the address range 0x0000 to 0x0FFF, the decoder logic would assert PSEL1 when PADDR is within this range. Similarly, if Slave 2 is assigned the address range 0x1000 to 0x1FFF, the decoder logic would assert PSEL2 when PADDR is within this range.

In systems where the APB bridge is connected to a higher-performance bus such as AHB (Advanced High-performance Bus) or AXI (Advanced eXtensible Interface), the address decoding process is typically handled by the bridge. The bridge decodes the address from the higher-performance bus (e.g., HADDR for AHB or AxADDR for AXI) and generates the appropriate PSEL signal for the targeted APB slave. The bridge also ensures that the PSEL signal is asserted only when a valid transaction is initiated on the higher-performance bus (e.g., when HTRANS is NONSEQ or SEQ for AHB, or when an xVALID/xREADY handshake completes for AXI).

Interconnect Behavior and Slave Response in APB Systems

The interconnect in an APB system plays a crucial role in routing transactions between the master and the appropriate slave. The interconnect is responsible for decoding the address (PADDR) provided by the master and generating the appropriate PSEL signal for the targeted slave. Additionally, the interconnect routes the response signals (PRDATA, PREADY, and PSLVERR) from the targeted slave back to the master.

The behavior of the interconnect can vary depending on the specific implementation. In some systems, the interconnect may generate individual APB ports for each slave, with each port having its own PSEL, PADDR, PWDATA, PWRITE, PENABLE, PRDATA, PREADY, and PSLVERR signals. In this case, the interconnect handles all the address decoding and signal routing internally, and the user does not need to implement any external logic.

In other systems, the interconnect may generate a single APB "Requester" interface with one or more PSEL lines. In this case, the user is responsible for implementing external logic to decode the address and generate the individual PSEL signals for each slave. The user is also responsible for routing the response signals (PRDATA, PREADY, and PSLVERR) from the targeted slave back to the master. This approach provides more flexibility but requires additional design effort.

The behavior of the slaves in an APB system is relatively simple. Each slave monitors its own PSEL signal and responds to transactions only when its PSEL signal is asserted. When a transaction is initiated, the master asserts the PENABLE signal to indicate that the address phase is complete and the data phase is beginning. The slave must then respond by asserting PREADY to indicate that it is ready to complete the transaction. If the transaction is a read, the slave provides the requested data on the PRDATA signal. If the transaction is a write, the slave captures the data from the PWDATA signal.

If the slave encounters an error during the transaction, it can assert the PSLVERR signal to indicate that an error has occurred. The master can then take appropriate action based on the error signal. It is important to note that the APB protocol does not support burst transactions, so each transaction is treated as an individual transfer. This simplifies the design of the slaves, as they do not need to handle complex burst sequences.

Implementing APB Communication with Single Master and Multiple Slaves

To implement an APB system with a single master and multiple slaves, the following steps should be taken:

1. Define the Address Map: The first step is to define the address map for the system. This involves assigning a unique address range to each slave. The address ranges should be contiguous and non-overlapping to ensure that each slave can be uniquely identified by its address range. For example, if the system has four slaves, the address map might be defined as follows:

   Slave	Address Range
   Slave 1	0x0000 – 0x0FFF
   Slave 2	0x1000 – 0x1FFF
   Slave 3	0x2000 – 0x2FFF
   Slave 4	0x3000 – 0x3FFF

2. Design the Address Decoder: The next step is to design the address decoder logic. The address decoder is responsible for decoding the address (PADDR) provided by the master and generating the appropriate PSEL signal for the targeted slave. The address decoder can be implemented using simple combinational logic, such as a set of comparators and AND gates. For example, the PSEL1 signal can be generated by comparing PADDR with the address range assigned to Slave 1:

   assign PSEL1 = (PADDR >= 12'h0000) && (PADDR <= 12'h0FFF);
   

   Similarly, the PSEL2 signal can be generated by comparing PADDR with the address range assigned to Slave 2:

   assign PSEL2 = (PADDR >= 12'h1000) && (PADDR <= 12'h1FFF);
   

   This process is repeated for each slave in the system.

3. Implement the Interconnect: The interconnect is responsible for routing the PSEL, PADDR, PWDATA, PWRITE, PENABLE, PRDATA, PREADY, and PSLVERR signals between the master and the appropriate slave. If the interconnect generates individual APB ports for each slave, the user does not need to implement any external logic. However, if the interconnect generates a single APB "Requester" interface, the user must implement external logic to decode the address and generate the individual PSEL signals for each slave. The user must also route the response signals (PRDATA, PREADY, and PSLVERR) from the targeted slave back to the master.

4. Design the Slaves: Each slave in the system must be designed to respond to transactions only when its PSEL signal is asserted. When a transaction is initiated, the slave must monitor the PENABLE signal and respond by asserting PREADY when it is ready to complete the transaction. If the transaction is a read, the slave must provide the requested data on the PRDATA signal. If the transaction is a write, the slave must capture the data from the PWDATA signal. If the slave encounters an error during the transaction, it must assert the PSLVERR signal to indicate that an error has occurred.

5. Verify the System: Once the system is implemented, it should be thoroughly verified to ensure that it functions correctly. This involves testing each slave to ensure that it responds correctly to transactions within its assigned address range. It also involves testing the address decoder and interconnect to ensure that they correctly route transactions to the appropriate slave. Additionally, the system should be tested for error conditions, such as invalid addresses or slave errors, to ensure that it handles these conditions correctly.

By following these steps, an APB system with a single master and multiple slaves can be successfully implemented. The key to a successful implementation is careful design of the address decoder and interconnect, as well as thorough verification of the system to ensure that it functions correctly under all conditions.