APB Slave Signal Sampling Timing for Read/Write Transactions

APB Slave Sampling of Address and Data Signals During Setup and Access Phases

The Advanced Peripheral Bus (APB) protocol, part of the ARM AMBA (Advanced Microcontroller Bus Architecture) family, is a simple yet robust interface for connecting low-bandwidth peripherals to a system-on-chip (SoC). A common challenge in APB-based designs is determining the correct timing for sampling address and data signals during read and write transactions. This issue is particularly critical when designing APB slaves that must ensure data integrity and protocol compliance while minimizing latency.

The APB protocol defines two phases for each transaction: the Setup Phase and the Access Phase. During the Setup Phase, the master asserts the PSEL signal to select the slave and provides the address (PADDR), write data (PWDATA, if applicable), and control signals (PWRITE). In the Access Phase, the master asserts PENABLE, and the slave must respond with PREADY and, for read transactions, PRDATA. The timing of when the slave samples the address and data signals directly impacts the transaction’s correctness and efficiency.

Incorrect sampling can lead to protocol violations, data corruption, or unnecessary delays. For example, if the slave samples PADDR or PWDATA too early or too late, it may misinterpret the transaction or fail to capture valid data. Similarly, if PRDATA is not driven at the correct time, the master may sample invalid or stale data. Understanding the precise timing requirements for sampling and driving these signals is essential for designing compliant and efficient APB slaves.

Control Signal Sampling at End of Setup Phase and Data Sampling in Access Phase

The APB protocol specifies that control signals, including PADDR and PWRITE, should be sampled by the slave at the end of the Setup Phase. This ensures that the slave has accurate information about the transaction type (read or write) and the target address before the Access Phase begins. Sampling these signals at the end of the Setup Phase allows the slave to prepare for the upcoming transaction, such as decoding the address or configuring internal logic.

For write transactions, the slave can sample PWDATA either at the end of the Setup Phase or during the Access Phase. Since PWDATA is guaranteed to remain stable throughout the transaction, the exact sampling point is less critical. However, sampling PWDATA during the Access Phase aligns with the protocol’s intent, as it provides the slave with an additional cycle to process the incoming data.

For read transactions, the slave must drive PRDATA during the Access Phase. The master samples PRDATA at the end of the Access Phase, just before PENABLE is deasserted. This means the slave must ensure that PRDATA is valid and stable during the Access Phase. If the slave requires additional time to fetch the data, it can assert PREADY low to extend the Access Phase. However, for optimal performance, the slave should aim to provide valid PRDATA within a single Access Phase cycle.

The relationship between signal sampling and driving is crucial for maintaining protocol compliance. For example, if the slave samples PADDR at the end of the Setup Phase, it can begin fetching the corresponding data immediately, ensuring that PRDATA is ready during the Access Phase. Similarly, for write transactions, sampling PWDATA during the Access Phase allows the slave to validate the data before writing it to the target register or memory location.

Optimizing APB Slave Design for Two-Cycle Transactions

To achieve two-cycle transactions, the APB slave must be designed to sample control signals at the end of the Setup Phase and drive PRDATA during the Access Phase. This requires careful synchronization of internal logic to ensure that all signals are processed and driven within the required timing constraints.

For write transactions, the slave can sample PWDATA during the Access Phase and write it to the target location in the same cycle. Since PWDATA is stable throughout the transaction, this approach minimizes latency without risking data corruption. The slave should assert PREADY high during the Access Phase to indicate that the write operation is complete.

For read transactions, the slave must sample PADDR at the end of the Setup Phase and begin fetching the corresponding data immediately. This allows the slave to drive valid PRDATA during the Access Phase, completing the transaction in two cycles. If the slave cannot provide valid PRDATA within a single Access Phase cycle, it must assert PREADY low to extend the transaction. However, this should be avoided whenever possible to maintain optimal performance.

In designs where PREADY is always driven high, the slave must ensure that PRDATA is valid during the Access Phase. This can be achieved by pre-fetching data based on the address sampled at the end of the Setup Phase. For example, the slave can use a register or buffer to store the fetched data, ensuring that it is available when needed during the Access Phase. This approach requires careful timing analysis to ensure that the data is ready in time.

The following table summarizes the key timing requirements for APB slave signal sampling and driving:

By adhering to these timing requirements, the APB slave can ensure protocol compliance and optimize transaction latency. This approach is particularly important in high-performance systems where minimizing bus latency is critical.

In conclusion, the correct timing for sampling and driving APB signals is essential for designing compliant and efficient APB slaves. By sampling control signals at the end of the Setup Phase and driving PRDATA during the Access Phase, the slave can achieve two-cycle transactions while maintaining data integrity and protocol compliance. Careful design and timing analysis are required to ensure that all signals are processed and driven within the required constraints, particularly in designs where PREADY is always driven high.