ARM CHI Protocol: Clean Cache Line Visibility and SnpAttr Transactions
The ARM Coherent Hub Interface (CHI) protocol is a critical component in ensuring data coherency across multiple requesters and caches in a system. One of the key challenges in implementing CHI is managing the visibility of clean cache lines when transactions with different SnpAttr values are involved. The issue revolves around the behavior of clean cache lines (UC or SC) in a fully coherent cache when accessed by requesters using transactions with SnpAttr = 0. Specifically, the protocol mandates that a clean cache line should not be made visible to a requester using a transaction with SnpAttr = 0 if that location has been updated by another transaction with SnpAttr = 0 after the cache line was allocated into the fully coherent cache.
This requirement is designed to prevent data inconsistency and ensure that all requesters have a coherent view of the memory. However, the interaction between SnpAttr = 0 and SnpAttr = 1 transactions, along with the state transitions of cache lines (Clean to Dirty), can lead to complex scenarios that are difficult to debug and understand. The core of the issue lies in the timing and conditions under which a clean cache line can be made visible to a requester using SnpAttr = 0, especially when the cache line has been modified by another transaction.
The problem becomes more pronounced when multiple requesters (RN-F1, RN-F2, RN-F3) are involved, each issuing different types of transactions (WriteNoSnpFull, ReadUnique) with varying SnpAttr values. The system must ensure that the visibility of the cache line is maintained correctly, especially when the line transitions from Clean to Dirty and moves between different levels of the cache hierarchy (e.g., from a fully coherent cache to the System Level Cache (SLC)).
SnpAttr = 0 Transactions and Cache Line State Transitions
The root cause of the issue lies in the interaction between SnpAttr = 0 transactions and the state transitions of cache lines in a fully coherent cache. When a clean cache line is allocated into the fully coherent cache, it can be accessed by requesters using SnpAttr = 0 transactions. However, if the cache line is subsequently updated by another transaction with SnpAttr = 0, the protocol requires that the updated cache line should not be made visible to the original requester using SnpAttr = 0. This is to prevent the requester from seeing stale data.
The confusion arises from the fact that SnpAttr = 0 transactions are allowed to snoop the coherent cache, but they are not required to. This means that a requester using SnpAttr = 0 can potentially access a clean cache line, but if the line has been modified by another transaction with SnpAttr = 0, the original requester should not see the updated data. This creates a scenario where the visibility of the cache line is dependent on the sequence of transactions and the state of the cache line.
Another contributing factor is the transition of the cache line from Clean to Dirty. When a requester (RN-F1) issues a WriteNoSnpFull transaction with SnpAttr = 0, the cache line is updated and becomes Dirty. This Dirty line is then moved to the System Level Cache (SLC). When another requester (RN-F2) issues a ReadUnique transaction, the Dirty line is moved from the SLC to RN-F2. At this point, the Dirty line is visible to the fully coherent requester (RN-F2), but the original requester (RN-F1) should not be able to access the Dirty line using a transaction with SnpAttr = 0.
The complexity increases when a new requester (RN-F3) attempts to access the location using a transaction with SnpAttr = 0. Since the line is now Dirty, the protocol mandates that the Dirty line should not be visible to the new requester using SnpAttr = 0. This requires the Home Node (HN-F) to snoop RN-F2 to maintain the visibility of the location for RN-F1, while ensuring that the Dirty line is not made visible to RN-F3.
Implementing Cache Coherency with SnpAttr Transactions and Data Synchronization
To address the issue of mismatched memory attributes and ensure proper cache coherency, the following troubleshooting steps and solutions can be implemented:
1. Understanding SnpAttr Transactions and Cache Line States
The first step in resolving the issue is to thoroughly understand the behavior of SnpAttr transactions and the state transitions of cache lines. SnpAttr = 0 transactions are allowed to snoop the coherent cache but are not required to, while SnpAttr = 1 transactions are required to snoop any RN-Fs that could have the cache line. This distinction is crucial in determining the visibility of cache lines to different requesters.
When a clean cache line is allocated into the fully coherent cache, it can be accessed by requesters using SnpAttr = 0 transactions. However, if the cache line is updated by another transaction with SnpAttr = 0, the protocol requires that the updated cache line should not be made visible to the original requester using SnpAttr = 0. This ensures that the original requester does not see stale data.
2. Managing Cache Line Transitions from Clean to Dirty
The transition of a cache line from Clean to Dirty is a critical event that must be managed carefully to maintain cache coherency. When a requester (RN-F1) issues a WriteNoSnpFull transaction with SnpAttr = 0, the cache line is updated and becomes Dirty. This Dirty line is then moved to the System Level Cache (SLC). At this point, the Dirty line is no longer visible to requesters using SnpAttr = 0 transactions.
When another requester (RN-F2) issues a ReadUnique transaction, the Dirty line is moved from the SLC to RN-F2. The Dirty line is now visible to the fully coherent requester (RN-F2), but the original requester (RN-F1) should not be able to access the Dirty line using a transaction with SnpAttr = 0. This requires the Home Node (HN-F) to snoop RN-F2 to maintain the visibility of the location for RN-F1, while ensuring that the Dirty line is not made visible to RN-F3.
3. Implementing Data Synchronization Barriers and Cache Management
To ensure that the visibility of cache lines is maintained correctly, data synchronization barriers and cache management techniques must be implemented. Data synchronization barriers (DSBs) ensure that all previous memory transactions are completed before proceeding to the next transaction. This is particularly important when dealing with SnpAttr = 0 transactions, as it ensures that the cache line is in the correct state before being accessed by another requester.
Cache management techniques, such as cache invalidation and cache cleaning, can also be used to maintain cache coherency. Cache invalidation ensures that any stale data in the cache is removed, while cache cleaning ensures that any modified data in the cache is written back to memory. These techniques are particularly useful when dealing with Dirty cache lines, as they ensure that the most up-to-date data is available to all requesters.
4. Debugging and Verifying Cache Coherency
Finally, debugging and verifying cache coherency is essential to ensure that the system is functioning correctly. This can be done using simulation tools and hardware debuggers to monitor the state of cache lines and the behavior of SnpAttr transactions. By carefully analyzing the sequence of transactions and the state transitions of cache lines, it is possible to identify and resolve any issues related to mismatched memory attributes and cache coherency.
In conclusion, the issue of mismatched memory attributes and cache coherency in the ARM CHI protocol is a complex problem that requires a deep understanding of SnpAttr transactions, cache line state transitions, and data synchronization techniques. By carefully managing the visibility of cache lines and implementing appropriate cache management techniques, it is possible to ensure that the system maintains cache coherency and operates correctly.
