ARM Core PMU and DSU_PMU: Differences, Interactions, and Best Practices

ARM Core PMU and DSU_PMU: Separate Hardware Components with Distinct Roles

The ARM Core Performance Monitoring Unit (Core PMU) and the DynamIQ Shared Unit Performance Monitoring Unit (DSU_PMU) are two distinct hardware components designed to monitor different aspects of system performance. The Core PMU is integrated within each ARM Cortex core and is responsible for tracking core-specific performance metrics such as instruction execution, cache hits/misses, and branch prediction accuracy. On the other hand, the DSU_PMU is part of the DynamIQ Shared Unit (DSU), which serves as the interconnect and power management hub for clusters of ARM cores. The DSU_PMU monitors system-level metrics such as interconnect traffic, power management events, and shared resource utilization.

The Core PMU and DSU_PMU do not share the same counters or registers. For instance, the Core PMU uses the PMCR_EL0 register to control its performance monitoring functionality, while the DSU_PMU uses the CLUSTERPMU_PMCR register. These registers are entirely separate and are accessed through different memory-mapped I/O addresses. The Core PMU focuses on per-core performance, while the DSU_PMU provides insights into cluster-wide and system-level behavior.

Despite their differences, the Core PMU and DSU_PMU can be used simultaneously without compromising each other’s results. However, care must be taken to ensure that the performance monitoring configurations do not interfere with each other. For example, enabling certain events on the Core PMU might increase cache contention, which could indirectly affect the metrics captured by the DSU_PMU. Understanding the distinct roles and interactions of these components is crucial for accurate performance analysis and optimization.

Potential Conflicts and Misconfigurations Between Core PMU and DSU_PMU

While the Core PMU and DSU_PMU are separate components, improper configuration or simultaneous usage can lead to misleading performance data. One common issue arises when developers assume that the counters in the Core PMU and DSU_PMU are synchronized or share resources. This misconception can lead to incorrect interpretations of performance metrics, especially in multi-core systems where the DSU_PMU monitors shared resources like the L3 cache or interconnect.

Another potential cause of conflicts is the omission of memory barriers or cache management instructions when accessing PMU registers. ARM architectures rely on explicit memory barriers to ensure that writes to control registers are completed before subsequent operations. Failing to use these barriers can result in inconsistent or incorrect counter values. Additionally, cache invalidation or flushing might be necessary when switching between Core PMU and DSU_PMU configurations to ensure that stale data does not affect performance measurements.

Resource contention is another factor to consider. For example, if the Core PMU is configured to monitor cache-related events, it might increase the load on the cache subsystem, which could indirectly affect the metrics captured by the DSU_PMU. Similarly, enabling high-frequency event sampling on both the Core PMU and DSU_PMU might lead to increased power consumption or thermal throttling, which could skew performance results.

Best Practices for Configuring and Using Core PMU and DSU_PMU

To avoid conflicts and ensure accurate performance monitoring, follow these best practices when working with the Core PMU and DSU_PMU:

1. Separate Configuration and Initialization: Always configure and initialize the Core PMU and DSU_PMU separately. Use the appropriate control registers (PMCR_EL0 for Core PMU and CLUSTERPMU_PMCR for DSU_PMU) and ensure that the configurations do not overlap or interfere with each other. For example, if you are monitoring cache events on the Core PMU, avoid enabling similar events on the DSU_PMU unless you explicitly want to compare core-level and cluster-level cache behavior.

2. Use Memory Barriers and Cache Management: When accessing PMU control registers, insert appropriate memory barriers (e.g., DSB, DMB) to ensure that writes are completed before proceeding. If you are switching between Core PMU and DSU_PMU configurations, consider invalidating or flushing the cache to prevent stale data from affecting your measurements.

3. Monitor Resource Contention: Be aware of potential resource contention between the Core PMU and DSU_PMU. For example, if you are monitoring cache-related events on both components, ensure that the increased load on the cache subsystem does not skew your results. Use performance counters to track resource utilization and adjust your configurations accordingly.

4. Leverage Event Filtering and Sampling: Both the Core PMU and DSU_PMU support event filtering and sampling. Use these features to focus on specific performance metrics and reduce the overhead of performance monitoring. For example, you can configure the Core PMU to monitor only branch mispredictions while using the DSU_PMU to track interconnect traffic.

5. Validate Results with Cross-Referencing: Cross-reference the results from the Core PMU and DSU_PMU to ensure consistency and accuracy. For example, if the Core PMU reports a high number of cache misses, verify this with the DSU_PMU’s cache-related metrics. Discrepancies between the two components might indicate misconfigurations or resource contention.

6. Optimize for Power and Thermal Constraints: Performance monitoring can increase power consumption and generate additional heat, especially when using high-frequency event sampling. Monitor power and thermal metrics using the DSU_PMU and adjust your configurations to avoid thermal throttling or excessive power draw.

7. Document and Share Configurations: Document your Core PMU and DSU_PMU configurations and share them with your team. This ensures consistency across different tests and makes it easier to reproduce results. Include details such as event selections, sampling rates, and memory barrier usage.

By following these best practices, you can effectively use the Core PMU and DSU_PMU to gain valuable insights into system performance without compromising accuracy or introducing conflicts. Understanding the distinct roles and interactions of these components is key to optimizing ARM-based systems and achieving reliable performance monitoring.