ARM Cortex-A15 LPAE Page Table Configuration and MAIR0.attr0 Interaction
The ARM Cortex-A15 processor, part of the ARMv7-A architecture, supports the Large Physical Address Extension (LPAE), which allows for 40-bit physical addressing and introduces a more complex memory translation system. One of the key components of this system is the Memory Attribute Indirection Register (MAIR), which defines memory attributes for different memory regions. The MAIR0 register, in particular, contains attributes for stage 1 memory translations, with each attribute field (attr0 to attr7) divided into two parts: the lower 4 bits (attrX[3:0]) define the inner cacheability attributes, while the upper 4 bits (attrX[7:4]) define the outer cacheability attributes.
In the context of the Cortex-A15, the Shareability (SH) field in the page table entry determines whether a memory region is marked as Non-shareable, Inner Shareable, or Outer Shareable. When a region is marked as Inner Shareable (SH[1:0] = 11), it is expected that the memory attributes defined by the inner cacheability bits (attr0[3:0]) will govern the behavior of the memory system for that region. However, in some configurations, the outer cacheability bits (attr0[7:4]) can also influence the system’s behavior, even when the region is explicitly marked as Inner Shareable. This interaction is not immediately intuitive and requires a deeper understanding of the Cortex-A15’s memory system architecture.
The Cortex-A15’s memory system is designed to support multiple levels of cache hierarchy, including integrated L1 and L2 caches within a cluster and potentially non-integrated L3 caches shared across multiple clusters. The inner and outer cacheability attributes in the MAIR0 register are intended to control the behavior of these different cache levels. However, the distinction between inner and outer cacheability is not always clear-cut, especially in systems where the cache hierarchy is complex or where hardware cache coherency mechanisms are in place.
When a memory region is marked as Inner Shareable, the expectation is that the inner cacheability attributes will control the behavior of the caches within the inner shareable domain. However, if the outer cacheability attributes are set to a non-zero value, they can still influence the system’s behavior, particularly if the outer caches are visible to masters within the inner shareable domain. This can occur in systems where the outer caches are non-integrated but still accessible to processors within the inner shareable domain, or where hardware cache coherency mechanisms extend beyond the inner shareable domain.
Hardware Cache Coherency and Shareability Domain Configuration
The behavior of the Cortex-A15’s memory system is heavily influenced by the configuration of the hardware cache coherency mechanisms and the shareability domains. In a typical multi-core system, each core within a cluster will have its own L1 cache, and the cores within the cluster will share an L2 cache. The L2 cache is considered part of the inner shareable domain, meaning that any memory accesses marked as Inner Shareable will be visible to all cores within the cluster. However, if the system includes an L3 cache that is shared across multiple clusters, the L3 cache may be considered part of the outer shareable domain.
The distinction between inner and outer shareable domains is important because it determines which caches are involved in maintaining coherency for a given memory region. When a memory region is marked as Inner Shareable, the hardware cache coherency mechanisms will ensure that any changes to the memory region are visible to all cores within the inner shareable domain. However, if the outer cacheability attributes are set to a non-zero value, the outer caches may also be involved in maintaining coherency, even if the memory region is marked as Inner Shareable.
This behavior can be particularly problematic in systems where the outer caches are non-integrated but still accessible to processors within the inner shareable domain. In such cases, the outer cacheability attributes can influence the behavior of the memory system, even if the memory region is explicitly marked as Inner Shareable. This can lead to unexpected behavior, such as cache coherency issues or performance bottlenecks, particularly if the outer caches are not properly managed.
The configuration of the shareability domains and the hardware cache coherency mechanisms is critical to understanding why the outer cacheability attributes can affect the behavior of the memory system, even when the memory region is marked as Inner Shareable. In some systems, the inner and outer shareable domains may overlap, or the hardware cache coherency mechanisms may extend beyond the inner shareable domain. In such cases, the outer cacheability attributes can still influence the behavior of the memory system, even if the memory region is explicitly marked as Inner Shareable.
Implementing Proper Cacheability and Shareability Configuration in Cortex-A15 Systems
To ensure that the Cortex-A15’s memory system behaves as expected, it is important to properly configure the cacheability and shareability attributes in the MAIR0 register and the page table entries. This involves understanding the hardware cache coherency mechanisms and the shareability domains in the system, as well as the interaction between the inner and outer cacheability attributes.
First, it is important to ensure that the inner cacheability attributes (attr0[3:0]) are set correctly for the memory region in question. These attributes control the behavior of the caches within the inner shareable domain, and they should be configured based on the desired cacheability behavior for the memory region. For example, if the memory region should be cached within the inner shareable domain, the inner cacheability attributes should be set to a value that enables caching.
Second, it is important to consider the outer cacheability attributes (attr0[7:4]) and their potential impact on the memory system. Even if the memory region is marked as Inner Shareable, the outer cacheability attributes can still influence the behavior of the memory system, particularly if the outer caches are visible to masters within the inner shareable domain. In such cases, it may be necessary to set the outer cacheability attributes to a value that ensures proper cache coherency and visibility across the entire memory system.
Finally, it is important to ensure that the shareability attributes in the page table entries are set correctly. The SH field in the page table entry determines whether the memory region is marked as Non-shareable, Inner Shareable, or Outer Shareable, and this setting should be consistent with the desired shareability behavior for the memory region. If the memory region should be visible only to cores within the inner shareable domain, the SH field should be set to Inner Shareable. However, if the memory region should be visible to all cores in the system, the SH field should be set to Outer Shareable.
In some cases, it may be necessary to experiment with different configurations of the cacheability and shareability attributes to determine the optimal settings for a given system. This may involve testing different combinations of inner and outer cacheability attributes and observing the behavior of the memory system. It may also involve consulting the system’s hardware documentation to understand the configuration of the hardware cache coherency mechanisms and the shareability domains.
In conclusion, the interaction between the inner and outer cacheability attributes in the Cortex-A15’s memory system can be complex, particularly in systems with multiple levels of cache hierarchy and hardware cache coherency mechanisms. Properly configuring the cacheability and shareability attributes in the MAIR0 register and the page table entries is critical to ensuring that the memory system behaves as expected. By understanding the hardware cache coherency mechanisms and the shareability domains, and by carefully configuring the cacheability and shareability attributes, it is possible to avoid unexpected behavior and ensure optimal performance in Cortex-A15 systems.
