GICv2 Initialization and Non-Secure Mode Interrupt Propagation
The ARM Cortex-A53 processor, when paired with the Generic Interrupt Controller version 2 (GICv2), presents a robust platform for managing interrupts in both secure and non-secure modes. However, initializing the GICv2 and ensuring proper interrupt propagation in non-secure mode can be challenging, especially when dealing with dual-core configurations. The primary issue revolves around the correct configuration of the GICv2 registers and the ARM Cortex-A53 core registers to ensure that interrupts are correctly routed, acknowledged, and handled.
In the context of non-secure mode, interrupts are categorized into Group 0 (Secure) and Group 1 (Non-Secure). The GICv2 controller uses the GICD_IGROUPRn registers to assign interrupts to these groups. At reset, all interrupts are assigned to Group 0, which means they are treated as secure interrupts. To enable non-secure interrupts, the GICD_IGROUPRn registers must be configured to assign the desired interrupts to Group 1. Additionally, the GICD_CTLR register must be configured to enable Group 1 interrupts.
The ARM Cortex-A53 core must also be configured to handle these interrupts. This involves setting up the Vector Base Address Register (VBAR_ELn) to point to the interrupt vector table, configuring the Secure Configuration Register (SCR_EL3) and Hypervisor Configuration Register (HCR_EL2) to route interrupts to the correct exception level, and clearing the interrupt masks in the Processor State (PSTATE) to allow the core to accept interrupts.
Misconfigured GICD_CTLR and GICC_CTLR Registers
One of the primary causes of interrupt propagation issues in the ARM Cortex-A53 with GICv2 is the misconfiguration of the GICD_CTLR and GICC_CTLR registers. The GICD_CTLR register controls the overall operation of the GICv2 distributor, including the enabling of Group 0 and Group 1 interrupts. If the GICD_CTLR.bit1 (Group 1 enable) is not set, non-secure interrupts will not be propagated to the CPU interface.
Similarly, the GICC_CTLR register, which controls the CPU interface, must be configured to enable Group 1 interrupts. If the GICC_CTLR.bit1 (Group 1 enable) is not set, the CPU interface will not signal non-secure interrupts to the core. Additionally, the FIQen bit in the GICC_CTLR register must be set to 1 to allow the CPU interface to signal FIQs.
Another critical aspect is the Priority Mask Register (GICC_PMR). This register determines the minimum priority level for interrupts to be signaled to the CPU. If the GICC_PMR is set to 0x0, all interrupts are masked. Therefore, it is essential to set the GICC_PMR to a value other than 0x0, typically 0xFF, to allow interrupts of all priority levels to be signaled.
Correcting Interrupt Handling and Ensuring Proper Return from Interrupt
To address the issues related to interrupt handling and return from interrupt, a detailed and methodical approach is required. The following steps outline the necessary actions to ensure proper interrupt handling and return from interrupt in the ARM Cortex-A53 with GICv2.
Step 1: Configure GICD_CTLR and GICC_CTLR Registers
The first step is to ensure that the GICD_CTLR and GICC_CTLR registers are correctly configured. The GICD_CTLR.bit1 must be set to enable Group 1 (Non-Secure) interrupts. Similarly, the GICC_CTLR.bit1 must be set to enable Group 1 interrupts at the CPU interface. Additionally, the FIQen bit in the GICC_CTLR register must be set to 1 to allow the CPU interface to signal FIQs.
Step 2: Set the Priority Mask Register (GICC_PMR)
The GICC_PMR must be set to a value other than 0x0 to allow interrupts to be signaled to the CPU. A typical value to use is 0xFF, which allows interrupts of all priority levels to be signaled.
Step 3: Configure the Vector Base Address Register (VBAR_ELn)
The VBAR_ELn register must be configured to point to the interrupt vector table. This ensures that the core jumps to the correct location when an interrupt occurs. The vector table must contain the appropriate exception handlers for the interrupts being used.
Step 4: Configure the Secure Configuration Register (SCR_EL3) and Hypervisor Configuration Register (HCR_EL2)
The SCR_EL3 and HCR_EL2 registers control the routing of interrupts to the correct exception level. The SCR_EL3.IRQ and SCR_EL3.FIQ bits must be set to route IRQs and FIQs to the correct exception level. Similarly, the HCR_EL2.IMO and HCR_EL2.FMO bits must be configured to route virtual interrupts to the correct exception level.
Step 5: Clear the Interrupt Masks in the Processor State (PSTATE)
The PSTATE.I and PSTATE.F bits must be cleared to allow the core to accept IRQs and FIQs, respectively. This ensures that the core is not masking the interrupts that are being signaled by the GICv2.
Step 6: Configure the GICD_IGROUPRn, GICD_ITARGETSRn, GICD_IPRIORITY, and GICD_ISENABLERn Registers
For each interrupt being used, the GICD_IGROUPRn register must be configured to assign the interrupt to Group 1 (Non-Secure). The GICD_ITARGETSRn register must be configured to set the target CPU for the interrupt (only required for SPIs, INTIDs 32 and up). The GICD_IPRIORITY register must be configured to set the priority of the interrupt, ensuring that it is higher than the value set in the GICC_PMR. Finally, the GICD_ISENABLERn register must be configured to enable the interrupt.
Step 7: Implement the Interrupt Service Routine (ISR) and Ensure Proper Return from Interrupt
The ISR must be implemented to handle the interrupt and perform the necessary actions. At the end of the ISR, the End of Interrupt (EOI) must be issued to the GICv2 to indicate that the interrupt has been handled. This is done by writing to the GICC_EOIR register.
To ensure proper return from interrupt, the ISR must restore the context of the interrupted program. This includes restoring the program counter (PC), processor state (PSTATE), and any other registers that were modified during the ISR. The ERET instruction is used to return from the interrupt and resume normal execution.
Step 8: Debugging and Verification
If the interrupts are still not being handled correctly, it is essential to verify the configuration of the GICv2 and ARM Cortex-A53 registers. This can be done by reading back the registers and ensuring that they are set to the expected values. Additionally, debugging tools such as JTAG can be used to step through the code and verify that the ISR is being executed correctly and that the EOI is being issued.
Step 9: Handling Nested Interrupts and Priority Inversion
In systems where nested interrupts are possible, it is essential to handle priority inversion and ensure that higher-priority interrupts are not blocked by lower-priority interrupts. This can be achieved by configuring the GICD_IPRIORITY registers
