ARM Cortex-A55 Cache Coherency and MMU Page Table Entry Updates

ARM Cortex-A55 MMU Page Table Entry Updates and Cache Coherency Requirements

The ARM Cortex-A55 processor, like many modern ARM cores, relies on a Memory Management Unit (MMU) to handle virtual-to-physical address translation. The MMU uses page tables stored in memory to perform these translations. When a page table entry (PTE) is modified, the MMU must be able to observe the updated entry to ensure correct address translation. However, the interaction between the CPU core, the cache subsystem, and the MMU can introduce subtle issues, particularly when dealing with cache coherency and memory attributes. This post delves into the specific scenario where a modified page table entry requires cache maintenance operations to ensure correct MMU behavior, even in a uniprocessor system.

The core issue revolves around the necessity of flushing the data cache after modifying a page table entry. The ARM Cortex-A55 processor, operating in AArch32 mode with the MMU configured for Write-Back (WB) cacheable memory attributes, may fail to observe updated page table entries unless a cache maintenance operation is performed. This behavior is counterintuitive, as one might expect the MMU to automatically observe changes made by the same CPU core. The discussion also highlights the importance of correctly configuring the MMU’s memory attributes and the differences between cache maintenance operations like DCCMVAC (Data Cache Clean by Virtual Address to Point of Coherency) and DCCMVAU (Data Cache Clean by Virtual Address to Point of Unification).

Misconfigured MMU Memory Attributes and Cache Coherency

The primary cause of the issue lies in the misconfiguration of the MMU’s memory attributes, specifically the Inner and Outer Cacheability settings. The ARM Cortex-A55 MMU relies on the memory attributes defined in the Translation Table Base Register (TTBR) to determine how it accesses page tables. These attributes include cacheability and shareability domains, which dictate whether the MMU accesses memory through the cache or directly from main memory.

In the discussed scenario, the MMU was incorrectly configured with "Inner Write-Through" cacheability instead of "Inner Write-Back." This misconfiguration caused the MMU to bypass the cache when accessing page table entries, leading to inconsistencies between the CPU core’s view of memory (which was cached) and the MMU’s view (which was uncached). As a result, the MMU failed to observe updates made to page table entries by the CPU core, necessitating a cache flush operation to ensure coherency.

The ARM Cortex-A55 processor treats memory as cached only if both the Inner and Outer cacheability attributes are set to Write-Back. If either attribute is misconfigured, the MMU may access memory uncached, leading to coherency issues. Additionally, the MMU’s Inner Cacheability settings are derived from specific bits in the TTBR, and a misalignment in these bits can result in incorrect memory attributes.

The distinction between DCCMVAC and DCCMVAU also plays a critical role in understanding the issue. DCCMVAC ensures that the cache line is cleaned to the point of coherency, meaning that all observers in the system (including the MMU) can see the updated data. In contrast, DCCMVAU only cleans the cache line to the point of unification, which may not be sufficient to ensure that the MMU observes the updated page table entry. This explains why DCCMVAC resolves the issue while DCCMVAU does not.

Correcting MMU Configuration and Implementing Cache Maintenance

To resolve the issue, the following steps must be taken:

1. Verify and Correct MMU Memory Attributes: Ensure that the MMU’s Inner and Outer cacheability attributes are correctly configured as Write-Back. For the ARM Cortex-A55, this means setting both the Inner and Outer attributes to Write-Back in the TTBR. Specifically, the IRGN (Inner Region) and ORGN (Outer Region) bits must be configured correctly. The IRGN bits are derived from specific bits in the TTBR, and any misalignment in these bits can result in incorrect memory attributes. Double-check the bit order and ensure that the correct values are written to the TTBR.

2. Perform Cache Maintenance Operations: If the MMU is correctly configured but the issue persists, perform a cache maintenance operation after modifying a page table entry. Use the DCCMVAC instruction to clean the cache line to the point of coherency, ensuring that the MMU can observe the updated entry. This step is particularly important in systems where the MMU and CPU core share the same cache hierarchy but may have different views of memory due to cache coherency issues.

3. Ensure Proper Memory Barriers: Use memory barrier instructions to enforce the correct ordering of memory operations. After writing a new page table entry, insert a Data Synchronization Barrier (DSB) to ensure that the write is visible to all observers, including the MMU. Follow this with an Instruction Synchronization Barrier (ISB) to ensure that the updated page table entry is visible to subsequent instruction fetches.

4. Invalidate TLB Entries: After updating a page table entry, invalidate the corresponding TLB entry to ensure that the MMU uses the updated translation. Use the TLBI (TLB Invalidate) instruction with the appropriate virtual address and address space identifier (ASID) if applicable. Follow this with a DSB to ensure completion of the TLB invalidation.

5. Validate System Configuration: In a multiprocessor system, ensure that all cores are configured consistently with respect to memory attributes and cache coherency. Use shareability attributes to define the coherency domain for page table entries and ensure that all cores observe updates correctly.

By following these steps, the issue of the MMU failing to observe updated page table entries can be resolved. The key takeaway is that even in a uniprocessor system, cache coherency and memory attribute configuration play a critical role in ensuring correct MMU behavior. Properly configuring the MMU and performing cache maintenance operations as needed can prevent subtle and hard-to-debug issues in ARM-based embedded systems.