ARM Cortex-A55 Core Startup Failure in AArch32-to-AArch64 Transition via PSCI
The issue at hand involves the failure of the second core (Core 1) to start executing code when initiated from Core 0 in AArch32 mode using the ARM PSCI (Power State Coordination Interface) interface. Core 0 successfully sends the CPU_ON command to Core 1, which is expected to run in AArch64 mode. However, Core 1 does not begin executing the intended code, despite the CPU_ON command returning a success status (0) initially and a pending status (-5) on subsequent attempts. This suggests that Core 1 is attempting to start but is failing at an early stage, likely before executing any instructions from the provided firmware.
PSCI Interface and Core Initialization Sequence
The PSCI interface is a standardized method for managing power states and core initialization in ARM-based systems. The CPU_ON function is used to power on a secondary core and start it executing code at a specified entry point. In this scenario, Core 0 is operating in AArch32 mode, while Core 1 is intended to run in AArch64 mode. The transition between these execution states is a critical point where issues can arise.
When Core 0 issues the CPU_ON command, it provides an entry point address for Core 1 to begin execution. The entry point address must be correctly aligned with the execution state (AArch64) and the memory map of the system. If the entry point is incorrect or if there are issues with the memory map, Core 1 may fail to start executing code.
Execution State Transition and Core Synchronization
The transition from AArch32 to AArch64 execution states involves several architectural considerations. The ARMv8 architecture allows for cores to operate in either AArch32 or AArch64 mode, but the transition between these states must be handled carefully. When Core 0, operating in AArch32 mode, initiates Core 1 to run in AArch64 mode, the system must ensure that the execution state is correctly set up before Core 1 begins executing instructions.
One potential issue is the synchronization between the cores. Core 0 must ensure that all necessary setup, such as setting up the exception level (EL) and the execution state, is complete before Core 1 starts executing. If Core 1 attempts to execute instructions before the execution state is properly configured, it may fail to start correctly.
Memory Map and Entry Point Configuration
The memory map of the system plays a crucial role in the core initialization process. The entry point address provided to Core 1 must be valid and accessible in the AArch64 execution state. If the entry point address is incorrect or if there are issues with the memory map, Core 1 may fail to start executing code.
Additionally, the memory map must be consistent between the AArch32 and AArch64 execution states. If there are discrepancies in the memory map between these states, Core 1 may encounter issues when attempting to access memory or execute instructions.
Memory Map Inconsistencies and Execution State Misconfiguration
Memory Map Inconsistencies Between AArch32 and AArch64
One of the primary causes of the issue could be inconsistencies in the memory map between the AArch32 and AArch64 execution states. The memory map defines how the processor accesses memory, including the location of code, data, and peripherals. If the memory map is not consistent between the two execution states, Core 1 may fail to access the necessary memory regions when it starts executing in AArch64 mode.
For example, if the entry point address provided to Core 1 is valid in the AArch32 memory map but not in the AArch64 memory map, Core 1 will fail to start executing code. Similarly, if the memory regions containing the firmware for Core 1 are not accessible in the AArch64 execution state, Core 1 will not be able to execute the intended code.
Execution State Misconfiguration During Core Initialization
Another potential cause of the issue is the misconfiguration of the execution state during core initialization. When Core 0 initiates Core 1, it must ensure that the execution state is correctly set up before Core 1 begins executing instructions. This includes setting the appropriate exception level (EL) and ensuring that the execution state is correctly configured for AArch64.
If the execution state is not properly configured, Core 1 may fail to start executing code. For example, if Core 1 is initialized in AArch32 mode instead of AArch64 mode, it will not be able to execute the AArch64 code provided in the firmware. Similarly, if the exception level is not correctly set, Core 1 may encounter issues when attempting to execute instructions.
PSCI Implementation and Firmware Compatibility
The implementation of the PSCI interface and the compatibility of the firmware with the ARMv8 architecture could also be contributing factors. The PSCI interface must be correctly implemented to ensure that the CPU_ON command properly initializes Core 1 and sets up the execution state. If there are issues with the PSCI implementation, Core 1 may fail to start executing code.
Additionally, the firmware provided for Core 1 must be compatible with the ARMv8 architecture and the AArch64 execution state. If the firmware is not correctly configured for AArch64, Core 1 may fail to execute the intended code. This could include issues with the entry point address, the memory map, or the execution state configuration.
Verifying Memory Map Consistency and Execution State Configuration
Verifying Memory Map Consistency Between AArch32 and AArch64
To address potential memory map inconsistencies, it is essential to verify that the memory map is consistent between the AArch32 and AArch64 execution states. This involves ensuring that the entry point address provided to Core 1 is valid and accessible in both execution states. Additionally, the memory regions containing the firmware for Core 1 must be accessible in the AArch64 execution state.
One approach to verifying memory map consistency is to compare the memory maps used in the AArch32 and AArch64 execution states. This can be done by examining the memory map configuration in the firmware and ensuring that the same memory regions are accessible in both execution states. If discrepancies are found, the memory map should be adjusted to ensure consistency.
Configuring Execution State for AArch64
To ensure that the execution state is correctly configured for AArch64, it is necessary to verify that the exception level (EL) and execution state are properly set up before Core 1 begins executing instructions. This can be done by examining the initialization code in the firmware and ensuring that the execution state is correctly configured for AArch64.
One approach to configuring the execution state is to use the appropriate ARMv8 instructions to set the exception level and execution state. For example, the ERET (Exception Return) instruction can be used to transition to the desired exception level and execution state. Additionally, the SCTLR_ELx (System Control Register) should be configured to enable the AArch64 execution state.
Debugging PSCI Implementation and Firmware Compatibility
To address potential issues with the PSCI implementation and firmware compatibility, it is necessary to debug the PSCI interface and verify that the firmware is correctly configured for the ARMv8 architecture. This involves examining the PSCI implementation in the firmware and ensuring that the CPU_ON command is correctly initializing Core 1 and setting up the execution state.
One approach to debugging the PSCI implementation is to use a debugger to step through the initialization code and verify that the CPU_ON command is correctly executed. Additionally, the firmware should be examined to ensure that it is compatible with the ARMv8 architecture and the AArch64 execution state. This includes verifying the entry point address, the memory map, and the execution state configuration.
Implementing Data Synchronization Barriers and Cache Management
To ensure that Core 1 starts executing code correctly, it may be necessary to implement data synchronization barriers and cache management techniques. Data synchronization barriers ensure that all memory accesses are completed before proceeding, which can help prevent issues with memory access during core initialization. Cache management techniques, such as cache invalidation and cleaning, can help ensure that the cache is correctly configured for the AArch64 execution state.
One approach to implementing data synchronization barriers is to use the DSB (Data Synchronization Barrier) and ISB (Instruction Synchronization Barrier) instructions in the initialization code. These instructions ensure that all memory accesses and instructions are completed before proceeding. Additionally, cache management techniques, such as cache invalidation and cleaning, can be implemented using the appropriate ARMv8 instructions.
Conclusion
The failure of Core 1 to start executing code when initiated from Core 0 in AArch32 mode using the PSCI interface is likely due to memory map inconsistencies, execution state misconfiguration, or issues with the PSCI implementation and firmware compatibility. By verifying memory map consistency, configuring the execution state for AArch64, debugging the PSCI implementation, and implementing data synchronization barriers and cache management techniques, it is possible to resolve the issue and ensure that Core 1 starts executing code correctly.
Summary of Troubleshooting Steps
| Step | Description |
|---|---|
| 1 | Verify memory map consistency between AArch32 and AArch64 execution states. |
| 2 | Configure the execution state for AArch64, including setting the appropriate exception level and enabling the AArch64 execution state. |
| 3 | Debug the PSCI implementation to ensure that the CPU_ON command is correctly initializing Core 1 and setting up the execution state. |
| 4 | Verify firmware compatibility with the ARMv8 architecture and the AArch64 execution state. |
| 5 | Implement data synchronization barriers and cache management techniques to ensure correct memory access and cache configuration. |
By following these troubleshooting steps, it is possible to identify and resolve the issues preventing Core 1 from starting correctly when initiated from Core 0 in AArch32 mode using the PSCI interface.
