PMCCNTR_EL0 Register Reads Zero Despite Proper Initialization
The core issue revolves around the Performance Monitor Counter Register (PMCCNTR_EL0) on the ARM Cortex-A72 processor not incrementing or returning a value of zero when read, despite seemingly correct initialization of the Performance Monitor Unit (PMU) registers. This issue is critical for developers relying on the PMU for precise timing measurements, performance profiling, or debugging in bare-metal or low-level environments. The PMU is a powerful tool for monitoring hardware events, including cycle counts, cache misses, and branch predictions, but its configuration is intricate and often prone to subtle misconfigurations.
The PMCCNTR_EL0 register is a 64-bit counter that increments with every processor cycle. It is part of the ARMv8-A architecture’s Performance Monitors Extension, which provides a suite of registers and counters for performance analysis. The Cortex-A72 implements this extension, but its behavior can be influenced by several factors, including privilege levels, secure state configurations, and register initialization sequences. When PMCCNTR_EL0 reads zero, it indicates that the counter is either disabled, not properly configured, or being blocked by higher-level system settings.
The initialization sequence described in the discussion involves setting up three key registers: PMUSERENR_EL0, PMCR_EL0, and PMCNTENSET_EL0. These registers control user-mode access, global PMU enablement, and individual counter enablement, respectively. While the reported register values after initialization appear correct (PMUSERENR_EL0 = 0xD, PMCR_EL0 = 0x41023001, PMCNTENSET_EL0 = 0x80000000), the PMCCNTR_EL0 counter remains at zero. This discrepancy suggests that the issue lies in either an incomplete initialization sequence, a misconfigured secure state, or an overlooked hardware dependency.
Secure State Configuration and PMU Enablement Dependencies
One of the most common causes of the PMCCNTR_EL0 counter not incrementing is improper configuration of the secure state and PMU enablement bits. The ARM Cortex-A72 supports both Secure and Non-secure states, and the PMU behavior can differ significantly between these states. The Secure Performance Monitors Enable (SPME) bit in the Monitor Debug Configuration Register (MDCR_EL3) plays a critical role in enabling PMU event counting in Secure state. If this bit is not set, the PMU counters may remain disabled, even if the PMCR_EL0 and PMCNTENSET_EL0 registers are configured correctly.
Another potential cause is the omission of the Performance Monitors Overflow Interrupt Enable bit in PMINTENSET_EL1. While this register primarily controls interrupt generation for counter overflow events, it can also influence counter operation. Disabling the overflow interrupt for the cycle counter (bit 31) is a necessary step to ensure uninterrupted counter operation. Failure to configure this register can result in the counter being held in a reset state or not incrementing as expected.
Additionally, the PMCCFILTR_EL0 register, which controls filtering options for the cycle counter, must be configured to allow counting in the desired execution environment. For example, setting bit 27 in PMCCFILTR_EL0 enables counting in Non-secure EL1 mode, which is essential for bare-metal applications running in EL1. If this bit is not set, the counter may not increment, even if other registers are properly configured.
Finally, the order of operations during PMU initialization can impact counter behavior. The ARM architecture requires specific sequences for enabling counters, resetting them, and starting measurements. For instance, the PMCR_EL0 register must be configured to enable the PMU (bit 0), reset all counters (bit 1), and start counting (bit 2). These operations must be performed in the correct sequence, with appropriate synchronization barriers (ISB instructions) to ensure proper hardware behavior.
Comprehensive PMU Initialization and Debugging Steps
To resolve the issue of PMCCNTR_EL0 reading zero, a comprehensive initialization sequence must be followed, ensuring all dependencies and configuration steps are addressed. Below is a detailed step-by-step guide to properly configure the PMU and enable the cycle counter on the ARM Cortex-A72.
Step 1: Enable Secure Performance Monitors
Begin by enabling the Secure Performance Monitors Enable (SPME) bit in the MDCR_EL3 register. This step is crucial for systems operating in Secure state or transitioning between Secure and Non-secure states. Use the following assembly code to set bit 17 of MDCR_EL3:
mrs x9, MDCR_EL3
orr x9, x9, #(1 << 17)
msr MDCR_EL3, x9
isb
Step 2: Disable Cycle Counter Overflow Interrupt
Next, disable the cycle counter overflow interrupt by clearing bit 31 in the PMINTENSET_EL1 register. This prevents the counter from being halted due to overflow conditions:
mov x9, #0
msr PMINTENSET_EL1, x9
isb
Step 3: Configure PMCCFILTR_EL0 for Desired Execution Environment
Set the appropriate filtering options in the PMCCFILTR_EL0 register to enable counting in the desired execution environment. For Non-secure EL1 mode, set bit 27:
mov x9, #(1 << 27)
msr PMCCFILTR_EL0, x9
isb
Step 4: Enable User-Mode Access to PMU Counters
Configure the PMUSERENR_EL0 register to allow user-mode access to the PMU counters. Set bits 0 (EN), 2 (ER), and 3 (CR) to enable access and counting:
mov x9, #(1 << 0 | 1 << 2 | 1 << 3)
msr PMUSERENR_EL0, x9
isb
Step 5: Enable and Reset PMU Counters
Configure the PMCR_EL0 register to enable the PMU, reset all counters, and start counting. Set bits 0 (E), 1 (P), and 2 (C) as follows:
mrs x9, PMCR_EL0
orr x9, x9, #(1 << 0 | 1 << 1 | 1 << 2)
msr PMCR_EL0, x9
isb
Step 6: Enable the Cycle Counter
Finally, enable the cycle counter by setting bit 31 in the PMCNTENSET_EL0 register:
mov x9, #(1 << 31)
msr PMCNTENSET_EL0, x9
isb
Debugging Tips
If the PMCCNTR_EL0 counter still reads zero after following the above steps, consider the following debugging tips:
- Verify the current exception level (EL) and security state using the CurrentEL and SCR_EL3 registers. Ensure the PMU configuration matches the execution environment.
- Check for unexpected resets or interruptions in the system that may be affecting the PMU counters.
- Use a debugger to single-step through the initialization sequence and inspect register values at each step.
- Consult the ARM Cortex-A72 Technical Reference Manual for additional details on PMU behavior and dependencies.
By following this comprehensive guide, developers can ensure proper configuration of the PMU and enable accurate cycle counting on the ARM Cortex-A72 processor.
