ARM Cortex-M4 Context Switching and INVPC Usage Fault Overview
The ARM Cortex-M4 processor is widely used in embedded systems for its balance of performance and power efficiency. One of its key features is the ability to handle exceptions and interrupts efficiently, which is crucial for real-time operating systems (RTOS) and context switching. However, improper handling of exception returns, particularly during context switching, can lead to HardFault exceptions. A specific case of this is the INVPC (Invalid PC Load) Usage Fault, which occurs when the processor attempts to return from an exception using the BX LR instruction but encounters an invalid Program Counter (PC) value or incorrect exception state.
The INVPC Usage Fault is triggered when the processor detects that the PC value being loaded is invalid or when the exception return process is corrupted. This can happen due to several reasons, such as an incorrect EXC_RETURN value, stack corruption, or improper handling of exception active bits in the System Control Block (SCB). In the context of the discussion, the issue arises during a context switch where the BX LR instruction is used to return from a HardFault handler that was triggered by an SVCall (Supervisor Call). The INVPC fault is indicated by the INVPC bit in the UsageFault Status Register (UFSR), and the processor enters the HardFault handler as a result.
Understanding the root cause of this issue requires a deep dive into the ARM Cortex-M exception handling mechanism, the role of the EXC_RETURN value, and the interaction between the stack, the Program Counter, and the exception active bits in the SCB. The following sections will explore the possible causes of this issue and provide detailed troubleshooting steps to resolve it.
Invalid EXC_RETURN Value and Exception Active Bit Mismanagement
The EXC_RETURN value is a critical component in the ARM Cortex-M exception handling mechanism. It is automatically loaded into the Link Register (LR) when an exception occurs and is used to determine the processor mode and stack pointer to be used upon exception return. The EXC_RETURN value also encodes information about whether the processor should return to Thread mode or Handler mode and whether the Main Stack Pointer (MSP) or Process Stack Pointer (PSP) should be used.
In the case of the INVPC Usage Fault, one of the primary causes is an invalid EXC_RETURN value. For example, if the EXC_RETURN value is 0xFFFFFFF1, the processor will attempt to return to Thread mode using the MSP. However, if the processor was in Handler mode before the exception, this would be an invalid return path, leading to a fault. Similarly, an EXC_RETURN value of 0xFFFFFFF9 indicates a return to Handler mode using the MSP, which would be invalid if the processor was in Thread mode before the exception.
Another potential cause is the mismanagement of exception active bits in the SCB->SHCSR (System Handler Control and State Register). The SHCSR contains bits that indicate whether specific exceptions, such as the SVCall or HardFault, are active. If an exception return is attempted while the corresponding exception active bit is still set, the processor may trigger an INVPC Usage Fault. This can occur if the exception active bit is not cleared before the return, or if the stack is corrupted, leading to an incorrect value being loaded into the Program Counter.
In the discussed scenario, the HardFault was triggered from an SVCall context, and the SYSCALLACT bit in the SCB->SHCSR register was still active when the BX LR instruction was executed. This caused the processor to attempt an exception return with an invalid state, leading to the INVPC Usage Fault. Clearing the SYSCALLACT bit before the exception return resolved the issue, highlighting the importance of proper exception state management.
Stack Corruption and ICI/IT Bit Invalidity During Exception Return
Stack corruption is another common cause of INVPC Usage Faults during exception returns. The ARM Cortex-M processor uses the stack to store the context (registers, Program Counter, and Program Status Register) during an exception. If the stack is corrupted, the values loaded during the exception return may be invalid, leading to a fault. This can happen due to buffer overflows, incorrect stack pointer manipulation, or other memory-related issues.
In the context of the discussed issue, stack corruption could have caused the stacked Program Counter (PC) or Program Status Register (PSR) to be incorrect. When the processor attempts to return from the exception, it loads the corrupted PC or PSR, leading to an INVPC Usage Fault. The stacked PC value is particularly important because it indicates the point where the faulting exception interrupted the main program. If this value is incorrect, the processor may attempt to execute an invalid instruction, triggering the fault.
Another potential cause of INVPC Usage Faults is the invalidity of the ICI/IT (Interrupt-Continuable Instruction/If-Then) bits in the PSR. The ICI/IT bits are
