ARM Cortex-R7 MPU DRACR Encoding Discrepancy Between TRM and ARMv7-AR Manual
The ARM Cortex-R7 processor, a high-performance real-time processor, relies heavily on its Memory Protection Unit (MPU) for defining memory regions and their attributes. The MPU Region Access Control Register (DRACR) is a critical component in configuring these memory attributes, including cache policies, shareability, and memory types. However, a significant discrepancy exists between the Technical Reference Manual (TRM) for the Cortex-R7 and the ARMv7-AR Architecture Reference Manual regarding the encoding of the DRACR register, specifically for the TEX[2:0], C, and B fields. This discrepancy has led to confusion among developers and engineers, particularly when implementing cache policies and memory attributes in real-time systems.
The TRM for the Cortex-R7 (DDI0458D) states that certain encodings for TEX[2:0], C, and B are reserved or unsupported, while the ARMv7-AR Architecture Reference Manual (DDI0406C) provides a different interpretation of these encodings, describing them as valid configurations for normal memory with specific cache policies. This inconsistency raises questions about the correct implementation of memory attributes and cache policies in the Cortex-R7, potentially leading to suboptimal system performance or even functional errors in embedded systems.
The core of the issue lies in the interpretation of the TEX[2:0], C, and B fields for the memory type and cache policy. Specifically, the TRM indicates that the encoding "TEX[2:0] = 000, C = 1, B = 0" is reserved, while the Architecture Manual describes it as "Outer and Inner Write-Through, no Write-Allocate." Similarly, the TRM omits the encoding for "TEX[2:0] = 000, C = 1, B = 1," whereas the Architecture Manual defines it as "Outer and Inner Write-Back, no Write-Allocate." These discrepancies are critical because they affect how developers configure the MPU for optimal performance and reliability in real-time applications.
Write-Through and Write-Back Cache Policy Support in Cortex-R7
The Cortex-R7 TRM explicitly states that the Write-Through cache policy is not supported, and all Inner Write-Back memory is treated as Write-Back Write-Allocate. This is a significant departure from the ARMv7-AR Architecture Reference Manual, which describes the Write-Through and Write-Back no Write-Allocate policies as valid configurations. The TRM further clarifies that the Cortex-R7 ignores any cache allocate hints for Inner Write-Back memory, dynamically switching to no Write-Allocate if more than three full cache lines are written in succession.
This behavior is unique to the Cortex-R7 and reflects its optimization for real-time systems, where deterministic performance is often prioritized over general-purpose flexibility. However, the lack of alignment between the TRM and the Architecture Manual creates confusion, particularly for developers who rely on the Architecture Manual as a universal reference for ARMv7-AR processors. The discrepancy also affects tools like the Lauterbach Trace32 debugger, which decodes MPU regions based on the Architecture Manual’s encoding, potentially leading to misinterpretations of the configured memory attributes.
The Write-Through cache policy, while not supported in the Cortex-R7, is a common feature in other ARM processors. It ensures that any write operation updates both the cache and the main memory simultaneously, providing a simple but less performant approach to cache coherency. In contrast, the Write-Back policy updates only the cache initially, deferring the write to main memory until the cache line is evicted. This improves performance but introduces complexity in maintaining cache coherency, especially in multi-core systems.
The Cortex-R7’s treatment of Inner Write-Back memory as Write-Back Write-Allocate, with dynamic switching to no Write-Allocate under specific conditions, is an optimization tailored for real-time systems. Write-Allocate ensures that a cache line is allocated on a write miss, which can improve performance for sequential writes. However, the dynamic switching to no Write-Allocate after three successive full cache line writes suggests a heuristic to balance performance and cache utilization, particularly in scenarios with high write throughput.
Resolving DRACR Encoding Discrepancies and Implementing Correct Cache Policies
To address the discrepancies between the Cortex-R7 TRM and the ARMv7-AR Architecture Reference Manual, developers must prioritize the TRM as the authoritative source for Cortex-R7-specific behavior. While the Architecture Manual provides a general framework for ARMv7-AR processors, the TRM contains implementation-specific details that are critical for correct configuration and optimal performance.
When configuring the MPU DRACR register, developers should avoid using the encodings marked as reserved or unsupported in the TRM, even if they are described differently in the Architecture Manual. Specifically, the encoding "TEX[2:0] = 000, C = 1, B = 0" should not be used, as it is reserved in the Cortex-R7. Similarly, the encoding "TEX[2:0] = 000, C = 1, B = 1" should be avoided, as the Cortex-R7 does not support the Write-Back no Write-Allocate policy described in the Architecture Manual.
For normal memory regions, developers should use the following encodings as defined in the Cortex-R7 TRM:
| TEX[2:0] | C | B | Description | Memory Type | Shareable |
|---|---|---|---|---|---|
| 000 | 0 | 0 | Strongly Ordered | Strongly Ordered | Yes |
| 000 | 0 | 1 | Shareable Device | Device | Yes |
| 001 | 0 | 0 | Outer and Inner Non-cacheable | Normal | S bit |
| 001 | 0 | 1 | Outer and Inner Write-Back | Normal | S bit |
For Inner Write-Back memory, developers should be aware that the Cortex-R7 treats all such memory as Write-Back Write-Allocate, ignoring any cache allocate hints. This behavior is consistent with the TRM and reflects the Cortex-R7’s optimization for real-time systems. If dynamic switching to no Write-Allocate is observed, it is a result of the Cortex-R7’s internal heuristic and does not require explicit configuration.
To ensure compatibility with debugging tools like Lauterbach Trace32, developers should document any deviations from the Architecture Manual’s encoding and provide clear explanations for the chosen configurations. This documentation is particularly important in team environments, where multiple developers may be working on different aspects of the system.
In conclusion, the discrepancies between the Cortex-R7 TRM and the ARMv7-AR Architecture Reference Manual highlight the importance of using processor-specific documentation when configuring critical system components like the MPU. By adhering to the TRM’s guidelines and understanding the Cortex-R7’s unique behavior, developers can avoid potential pitfalls and ensure optimal performance in their real-time systems.
