Author: David Moore

The Cortex-M0 processor from ARM is designed to provide an ultra low power 32-bit CPU solution for microcontroller and deeply embedded applications. The processor is optimized to deliver the best power vs performance ratio, making it ideal for power-constrained devices that need to balance processing capabilities with extended battery life. Low Power Design Philosophy The

Strongly ordered memory is a memory ordering model used in the ARMv6 and ARMv7 architectures to ensure correctness and consistency of data in concurrent and parallel programming. It provides stricter guarantees compared to weakly ordered memory by enforcing a total order on memory operations. This prevents issues like read-after-write hazards and ensures program correctness. Introduction

ARM Cortex-M processors can be configured with either a unified or separate memory address space for code and data. The choice impacts performance, software design, and memory protection capabilities. Unified Memory Address Space In the unified memory address space configuration, both code and data share the same logical address space. All memory access instructions like

The ARM Cortex-M series of microcontroller chips utilize a modified Harvard architecture. This architecture separates instruction and data memories into distinct address spaces, while still allowing tight coupling between the two for flexibility. The separation provides several advantages in embedded systems such as deterministic instruction fetch, higher performance, and simpler memory subsystem design. Overview of

The Arm architecture includes two important branch and link instructions – BL and BLX. These instructions allow you to branch or jump to a different part of your program, while also storing the return address so you can later return back to where you came from. In this article, we will demystify these instructions and

Interrupt latency is an important performance metric for real-time embedded systems built around Arm Cortex-M processors. It refers to the time elapsed from when an interrupt is generated to when the first instruction of the interrupt handler starts executing. Minimizing interrupt latency allows real-time tasks and events to be handled more responsively. This article provides

The ARM processor has several different processor modes that allow access to different resources and functionality. The current processor mode is stored in the Current Program Status Register (CPSR). By writing values to specific bits in the CPSR, the processor mode can be changed. This allows switching between modes like User mode, FIQ mode, IRQ

The ARM CPSR (Current Program Status Register) controls the processor operating mode and enables switching between different modes in ARM cores. The CPSR stores status and control information such as the ALU flags, current processor mode, and interrupts enabling/disabling. Changing the mode field in the CPSR allows switching between different processor modes. ARM Processor Modes