Arm

Serial Wire Viewer (SWV) is a real-time trace functionality that is available in Arm Cortex-M microcontrollers. It allows real-time data to be transmitted from the Cortex-M CPU to an external debug probe, which can capture the data for viewing and analysis on a host computer. The key benefit of SWV is that it enables non-intrusive…

The Flash Patch and Breakpoint (FPB) unit in Arm Cortex-M processors provides an efficient mechanism to rewrite flash memory contents and set code breakpoints for debugging and software patching purposes. This article provides a comprehensive overview of the FPB unit, how it works, its key features, configuration, and usage examples for patching code in flash…

The Arm Cortex-M series of processors feature a Debug Access Port (DAP) that provides debug capability and access to the processor’s internal state while it is running. The DAP uses a standard JTAG interface and allows debugging tools like GDB to halt, single-step, and examine registers and memory on the target device. This article will…

The Cortex-M3 processor provides multiple clock control features that allow significant power savings by slowing or stopping clocks when parts of the system are idle. Careful use of these features can extend battery life in portable applications or reduce heat and energy use in plugged-in systems. This article provides an overview of the clock control…

Sleep-on-exit is a feature in Cortex-M3 processors that allows the processor to automatically enter a low power sleep mode when exiting an ISR or exception handler. This reduces power consumption by avoiding unnecessary wakeups when handling short interrupt service routines. By enabling sleep-on-exit, the processor can go to sleep and wake up much faster between…

The WFI (Wait For Interrupt) and WFE (Wait For Event) instructions allow the Cortex-M3 processor to enter a low power state until a wakeup event occurs. This enables significant power savings in embedded systems through reducing dynamic power when the processor is idle. Contents Introduction Reducing power consumption is a key priority in many embedded…

The IDCODE is a 32-bit code that provides details about the device, including the version, manufacturer, and part number. When debugging Cortex devices, reading the IDCODE is one of the first things to do as it confirms you have a connection and provides key details about the target device. IDCODE Format The 32-bit IDCODE value…

The Cortex-M3 processor has advanced memory access capabilities through the use of caches and shared memory regions. However, these features also impose certain constraints that need to be understood when developing applications. Careful memory architecture design is required to avoid hazards from overlapped or out-of-order memory accesses. Instruction and Data Caches The Cortex-M3 instruction and…

The Instrumentation Trace Macrocell (ITM) is a tracing and debugging feature in Arm Cortex-M series processors. It provides a way to send profiling and diagnostic information from the Cortex-M CPU to a trace port on the processor. This allows for real-time tracing of software execution without halting or interrupting the processor. Overview of ITM The…

Debugging software on Arm Cortex-M devices requires configuring the CoreSight components like the Embedded Trace Macrocell (ETM), Trace Port Interface Unit (TPIU), Embedded Trace Buffer (ETB) etc. Choosing the right debugger and properly setting up the debug hardware is key to an efficient software debugging workflow. Overview of CoreSight Components in Cortex-M The Cortex-M series…