Arm

The JTAG-DP and SWJ-DP are two commonly used debug ports for ARM Cortex-M series microcontrollers. Both provide debug access and programming capabilities, but have some key differences. Overview of JTAG-DP and SWJ-DP JTAG-DP refers to the JTAG Debug Port, which utilizes the IEEE 1149.1 JTAG interface standard. It provides 4 pins for debug access –…

The Cortex-M System Design Kit supports a range of bus protocols that allow the Cortex-M processor to interface with peripheral devices and external memory. Selecting the right bus protocol is an important design consideration that impacts performance, power consumption, and ease of integration with hardware blocks. AMBA AHB-Lite The Advanced Microcontroller Bus Architecture (AMBA) AHB-Lite…

The Cortex-M3 processor offers a deep sleep mode that allows the system to enter an extremely low power state while retaining the contents of RAM. This allows maximum power savings while still providing fast wake-up times. Utilizing deep sleep mode properly is key to optimizing battery life in Cortex-M3 based devices. Introduction to Deep Sleep…

When compiling code for the ARM Cortex-M4 processor, you may encounter linker errors related to incompatible libraries or architecture mismatches. This usually happens when the compiler cannot find the correct libraries or is trying to link code compiled for a different architecture. Here are some tips for resolving these ld library and architecture errors when…

Cross-compiling for ARM can seem daunting at first, but with the right tools and techniques, it can be straightforward and efficient. Here are some tips to help you get started with ARM cross-compilation. Choose the Right Toolchain The first step is choosing the right toolchain for your needs. Popular options include: Consider factors like licensing,…

The Cortex-M3 memory map is divided into several regions, each with specific access behaviors. The Code region stores program instructions and is readable but not writable. The SRAM region stores data and is readable and writable. The Peripheral region maps to device registers and has read/write access that depends on the peripheral. The Cortex-M3 implements…

The Cortex-M3 memory system allows configuring memory regions to be shareable or non-shareable between processors. It also allows configuring cache policies for each region to specify whether the region is cached or bypassed. Proper configuration is important for system performance and determinism. Shareability The Cortex-M3 allows configuring memory regions as shareable or non-shareable. Shareable regions…

The ARM Cortex-A55 and Cortex-A76 are two of ARM’s most popular CPU cores used in mobile devices. The Cortex-A55 is ARM’s first 64-bit “little” CPU core, while the Cortex-A76 is a high-performance “big” CPU core. There are some key differences between these two cores: Intended Use Cases The Cortex-A55 is designed for power efficiency and…

The ARM Cortex-A76 is generally considered to be a very good mobile CPU core. It offers excellent performance and efficiency which makes it suitable for use in smartphones, tablets, and other mobile devices. Some key advantages of the Cortex-A76 include: Performance The Cortex-A76 delivers a significant performance boost over previous ARM cores like the Cortex-A73…

The ARM Cortex-A76 and Cortex-A77 are two of ARM’s most advanced high-performance CPU cores designed for mobile, computing, and infrastructure applications. Both cores are based on ARM’s DynamIQ technology and built on the 7nm manufacturing process, offering significant improvements in performance and efficiency over previous ARM CPU generations. The Cortex-A77 builds upon the Cortex-A76 design…