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The Flash Patch and Breakpoint (FPB) unit in Arm Cortex-M processors provides an efficient mechanism to rewrite flash memory contents and set code breakpoints for debugging and software patching purposes. This article provides a comprehensive overview of the FPB unit, how it works, its key features, configuration, and usage examples for patching code in flash
The Cortex-M3 memory map is divided into several regions, each with specific access behaviors. The Code region stores program instructions and is readable but not writable. The SRAM region stores data and is readable and writable. The Peripheral region maps to device registers and has read/write access that depends on the peripheral. The Cortex-M3 implements
The Cortex-M3 processor has a feature called Bit Banding that allows each individual bit in a word of memory to be referenced and manipulated as if it were a byte in memory. This provides faster read and write access to individual bits compared to using regular bitwise operations. The Bit Band regions map each bit
Bit-banding is a feature in some Arm Cortex processors that allows single bit modifications to be made to memory mapped peripherals without the overhead of a read-modify-write sequence. This provides an efficient mechanism to set or clear individual bits in registers. Bit-band regions map a complete word in memory to a single bit in the
The Cortex-M3 vector table contains the reset value and exceptions handlers that are executed when specific events occur. By default, the vector table is located at the start of the flash memory in Cortex-M3 devices. However, it is possible to relocate the vector table to a different location in the flash memory or SRAM. This
When debugging Cortex-M3 processors, developers have the option of using either a processor-only reset or a full reset. The choice depends on the specific debugging needs. A processor-only reset is faster but does not fully reset the system. A full reset takes longer but resets the entire system, which is sometimes necessary for debugging. What
The Cortex-M3 processor contains multiple reset domains that allow independent reset control of different modules within the system. Proper configuration and management of these reset domains is crucial for developing robust and reliable Cortex-M3 based systems. Introduction to Reset Domains A reset domain refers to a logical grouping of modules that share common reset control
The Cortex-M3 processor implements the ARM Thumb-2 instruction set architecture, which includes 16-bit and 32-bit instructions. The 16-bit instruction set provides a rotate right (ROR) instruction but not a rotate left (ROL) instruction. The 32-bit instruction set does include both ROR and ROL instructions. The main reason the 16-bit Thumb instruction set only has ROR
The ARM Cortex series of chips support conditional execution of instructions using the Compare and Branch instructions CBZ and CBNZ. These allow you to efficiently compare a register against zero and conditionally branch based on the result. This provides a way to implement conditional logic and flow control without having to explicitly compare and branch,
Indirect branching allows jumping to an address stored in a register, providing flexibility in control flow. The Arm instruction set includes two main indirect branch instructions – BX and BLX. This article will explain how they work and when to use each one. What is an Indirect Branch? An indirect branch occurs when the destination