Author: David Moore

The Cortex-M1 vector table allows developers to configure the stack size and heap size for an application. Properly setting these values can optimize memory usage and prevent stack overflows or heap allocation failures. This article provides a step-by-step guide to setting the stack and heap size in the vector table for Cortex-M1 chips. Overview of

The Cortex-M series of ARM processors are extremely popular in embedded systems due to their low cost, low power consumption, and excellent performance. All Cortex-M variants have built-in fault handling capabilities, with the HardFault exception being the catch-all fault handler for undefined faults not handled by other fault exceptions. While the HardFault mechanism is consistent

The ARM Cortex-M0 is a 32-bit RISC processor core designed for microcontroller applications. It is one of the most basic and low-power ARM processor cores, aimed at simple embedded devices that require minimal computing power and memory footprint. The Cortex-M0 operates at voltages ranging from 1.65V to 3.6V, depending on the specific implementation and silicon

Learning to program microcontroller units (MCUs) using makefiles and an ARM toolchain provides a powerful and flexible workflow for embedded development. Makefiles allow you to automate the build process while the ARM toolchain gives you access to the robust ARM Cortex architecture. With some setup and practice, you’ll be able to compile, flash, and debug

The ARM Cortex-M0 is one of the most popular microcontroller cores used in IoT and embedded devices today. It is an extremely energy-efficient 32-bit RISC processor optimized for low-cost and low-power applications. When looking at the performance of the Cortex-M0, one key metric is how many clock cycles it takes to execute common instructions like

Calculating the millions of instructions per second (MIPS) rating for an algorithm running on an ARM processor can provide useful insights into its performance and efficiency. The key steps are understanding the algorithm’s operations, determining the number of clock cycles for each operation on the target ARM chip, and factoring in the processor’s clock speed.

Implementing a loop position independent in ARM Cortex-M0+ requires utilizing the relative branch instructions available in the Thumb-2 instruction set. The key is to use PC-relative addressing rather than absolute jumps so that the target addresses do not need to change when the loop’s position in memory changes. Overview of Cortex-M0+ Branch Instructions The Cortex-M0+

The Cortex Microcontroller Software Interface Standard (CMSIS) DSP library provides a wide range of digital signal processing functions that are optimized for ARM Cortex-M processor-based microcontrollers. Using the CMSIS DSP library in Keil projects can help improve performance and reduce development time compared to coding the DSP algorithms from scratch. What is the CMSIS DSP

Yes, CMSIS stands for Cortex Microcontroller Software Interface Standard and it is a vendor-independent hardware abstraction layer for microcontrollers based on Arm Cortex processors. So CMSIS is essentially a library that provides a standard way to access the hardware features of Cortex-M processor-based microcontrollers from various Arm chip vendors. What is CMSIS? CMSIS defines interfaces

The ARM Cortex-M series of processors are extremely popular in embedded devices and IoT applications. They provide a good balance of performance, power efficiency and cost. Linux on the other hand is the most popular open-source operating system. Learning how to use the ARM Cortex-M processors with Linux allows developers to leverage the benefits of