Author: Eileen David

The ARM Cortex-M3 processor supports both little endian and big endian data storage formats. The endianness can be configured through the CPU’s control registers during start up. Choosing the right endianness format is important for performance and interoperability. Introduction to Endianness Endianness refers to the byte ordering used to store data in memory. There are

Disassembling ARM object files allows you to view the machine code instructions that were generated by the compiler. This can be useful for debugging, reverse engineering, and understanding how code executes on ARM processors. This guide will walk through the basic steps for disassembling ARM object files using common tools like objdump and GNU binutils.

The Controller Area Network (CAN) bus is a robust vehicle bus standard that allows microcontrollers and devices to communicate with each other within a vehicle without a host computer. It is a message-based protocol, designed originally for multiplex electrical wiring within automobiles to save on copper, but is also used in many other contexts. History

The ARM Cortex-M3 processor is a 32-bit processor, meaning its general purpose registers and main data bus are 32 bits wide. This allows it to process 32-bit data and memory addresses directly in a single cycle. Overview of ARM Cortex-M3 The ARM Cortex-M3 is a member of the Cortex-M series of ARM processors. It is

The Thumb instruction set is a compressed 16-bit instruction set that is supported by the ARM Cortex-M3 processor alongside the standard 32-bit ARM instruction set. The key benefit of Thumb is that it provides improved code density and reduced memory footprint compared to the 32-bit ARM code. This makes it well-suited for embedded applications where

Atomic operations, where a single instruction executes in an uninterruptible sequence, are essential for many embedded systems and microcontroller applications. The ARM Cortex M3 processor provides atomic read-modify-write instructions for 32-bit and 16-bit data types. However, single bit access presents challenges for atomicity. This article examines techniques for achieving atomic single bit writes on the

The Arm Cortex-M processors support several pre-indexed addressing modes that allow efficient access to arrays and structured data. These addressing modes automatically increment or decrement an index register as part of the address calculation, reducing code size and increasing performance when accessing sequential data structures or arrays. Overview of Pre-Indexed Addressing In pre-indexed addressing modes,

Debugging any microcontroller can be challenging, but debugging ARM Cortex processors like the Cortex-M1 and Cortex-M3 adds another layer of complexity. While both processors are based on the ARM architecture, there are key differences between the two that impact the debugging process. Core Architecture The Cortex-M1 uses the ARMv6-M architecture which is a simpler, smaller

When developing bare metal applications for Arm Cortex-M microcontrollers, determining the maximum stack usage is crucial for allocating sufficient stack memory and avoiding stack overflows. This article provides a detailed guide on techniques and tools for accurately measuring stack usage in bare metal Cortex-M apps. Introduction to Stack Usage in Cortex-M Apps In Cortex-M microcontrollers,

Understanding and optimizing stack usage is an important part of developing efficient software for Arm-based systems. The stack is a region of memory used to store temporary variables created by functions and invoked during program execution. Keeping stack usage low improves performance and helps prevent stack overflows that can cause crashes or undefined behavior. Arm’s