Author: Jamie Kellett

TrustZone security instructions in Arm Cortex-M series processors provide hardware-based security features to enable trusted execution environments and partition sensitive and non-sensitive application code and data. The key capabilities enabled by TrustZone include secure boot, authentication, encryption, and isolated execution of trusted software. Overview of Arm TrustZone Arm TrustZone technology creates a hardware-enforced secure world

Single-cycle I/O ports in Arm Cortex-M series microcontrollers allow data to be written to or read from the port in a single clock cycle. This makes them faster than multi-cycle I/O ports which require multiple clock cycles per access. The single-cycle ports improve performance for time-critical I/O operations. Overview of I/O Ports in Cortex-M The

When working with Xilinx’s Vitis tools to build projects targeting ARM Cortex-M1 processors, there are some common configuration mistakes that are easy to make. These misconfigurations can lead to hard-to-debug issues or problems getting your application to run properly on the target hardware. In this article, we’ll go over some of the most common pitfalls

For many years, x86 processors from companies like Intel and AMD have dominated the computing industry, powering the vast majority of laptops, desktops, and servers. More recently though, Arm-based processors have emerged as a growing challenger, appearing in smartphones, tablets, and even newer laptops like the Apple MacBook Pro. This has led to the question:

The ARM Cortex-M0+ processor is an ultra low power 32-bit RISC CPU core designed for microcontroller applications. It is part of ARM’s Cortex-M series of cores, and is their smallest and most energy efficient implementation, making it well suited for IoT edge devices and other battery powered applications where cost and power consumption are critical

The Cortex M0+ is an ultra-low power 32-bit ARM processor designed for simple and cost-sensitive embedded applications. With its reduced gate count, low leakage currents and efficient instruction set, the Cortex M0+ provides an optimal balance between performance, power consumption and cost. One of the key features of the Cortex M0+ is its General Purpose

The M0 SDK provides a way to load programs from external SPI flash rather than having the program reside in internal flash. This allows for larger programs beyond the size constraints of internal flash and offers more flexibility. Here is an overview of how to set up and use external SPI flash with M0 SDK:

To check firmware code coverage during RTL simulation for ARM Cortex-M0/M0+ cores, the main tools and techniques used are code coverage monitors built into the simulator, scripting to automate simulation runs, and coverage reports. The key steps are: 1. Selecting a Simulator with Coverage Monitoring The first step is choosing an RTL simulator that has

The Cortex-M3 processor from ARM is designed to be an extremely low power 32-bit microcontroller. Its power efficiency comes from multiple architectural design choices that aim to reduce power consumption during both active operation and idle periods. Power Saving Modes The Cortex-M3 has several low power modes that allow peripherals and CPU functionality to be

The ARM Cortex M3 processor is a 32-bit microcontroller CPU core designed for embedded applications requiring high performance and low power consumption. Some key features of the Cortex M3 include its Thumb-2 instruction set architecture, 3-stage pipeline, Memory Protection Unit, and low power sleep modes. Introduction to ARM Cortex M3 ARM Holdings introduced the Cortex