Author: Scott Allen

There are a few options available for acquiring Cortex-M1 and Cortex-M0 soft CPU cores to use in FPGA or ASIC designs. The main options are directly from ARM, from third-party IP vendors who license the cores from ARM, or develop your own soft core that is compatible with the ARM instruction set. Acquiring from ARM

The Cortex-M0 DesignStart soft core provides a low-cost entry point for exploring ARM’s Cortex-M0 processor IP. By combining the DesignStart core with the MPS2+ FPGA development board, users can quickly prototype and evaluate Cortex-M0 based systems. This combination offers an affordable option for learning about ARM’s most energy efficient Cortex processor. Overview of the Cortex-M0

Updating to the latest version of Xilinx Vivado can provide access to new features, improved performance, and bug fixes. However, it also often requires migrating existing projects to the new version. For ARM-based designs, this migration process can be tricky if not handled properly. Here are some tips for smoothly updating Vivado and migrating ARM

Configuring the memory map for a Cortex-M1 processor in a Pynq environment allows optimal utilization of the memory resources. A carefully planned memory layout ensures code and data are allocated appropriately for efficient execution. The key considerations include defining regions for code, data, peripherals, and ARM internals while accounting for cache and MMU behavior. Overview

The short answer is that while Arm is making inroads into areas traditionally dominated by x64 like servers and laptops, complete replacement is unlikely in the near future. x64 retains key advantages in performance and software ecosystem that will be difficult for Arm to overcome completely. However, Arm does have a chance to take significant

The battle between Arm and x86 architectures has been going on for decades in the CPU and microprocessor industry. With Arm based chips slowly making their way into PCs and servers, while x86 chips continue dominating desktops and data centers, many wonder how the two compare when it comes to performance. In terms of raw

The wake-up interrupt controller (WIC) in Arm Cortex-M series microcontrollers is a peripheral module that manages wake-up from low power modes. It allows the processor to be woken up from sleep and deep sleep modes when certain events or interrupts occur, enabling low power operation while still being able to respond to critical events. Overview

Breakpoint comparators are hardware debug features in Arm Cortex-M series microcontrollers that allow developers to set breakpoints based on data accesses rather than just instruction addresses. This enables more powerful and flexible debugging by pausing execution when specific memory addresses are accessed or certain values are present in registers or memory. Overview of Arm Cortex-M

Interrupt latency in Arm Cortex-M series microcontrollers refers to the time it takes for an interrupt request to be serviced after it is asserted. It is an important metric that impacts real-time response in embedded systems. Interrupt Handling in Cortex-M Arm Cortex-M microcontrollers have an interrupt-driven architecture. When an event like an external interrupt or

The instruction pipeline is a key feature of Arm Cortex-M series microcontrollers that allows them to achieve high performance despite their relatively simple in-order execution. In a nutshell, the instruction pipeline breaks down instruction execution into multiple stages, allowing multiple instructions to be in different stages of execution at the same time. This increases instruction