Author: System on Chips

ARM CHI Protocol and WriteEvictFull Opcode Behavior The ARM Coherent Hub Interface (CHI) protocol is a critical component of ARM’s system architecture, designed to manage cache coherency and data transfers between different nodes in a system. One of the key operations in the CHI protocol is the WriteEvictFull opcode, which is used to write back…

ARM Cache Invalidate Queue: A Hidden Mechanism in Multi-Core Systems In multi-core ARM systems, cache coherency is a critical aspect of ensuring that all cores have a consistent view of memory. One of the lesser-discussed mechanisms that play a role in maintaining this coherency is the "invalidate queue." The invalidate queue is a hardware structure…

ARM Cortex-A5 TLB VA-PA Mapping Challenges with Small Pages The ARM Cortex-A5 processor, based on the ARMv7 architecture, utilizes a Translation Lookaside Buffer (TLB) to accelerate virtual-to-physical address translation. The TLB is a critical component of the Memory Management Unit (MMU), and its proper functioning is essential for efficient memory access. However, decoding TLB entries,…

APB Protocol Timing and the Role of Dummy Cycles The Advanced Peripheral Bus (APB) protocol, part of the ARM Advanced Microcontroller Bus Architecture (AMBA), is designed for low-bandwidth, low-power peripheral communications. One of the key aspects of the APB protocol is its timing requirements, particularly the inclusion of dummy cycles between transfers. These dummy cycles,…

ARM Cortex-R5 PC Value Corruption in Wave Simulation The issue at hand involves the Program Counter (PC) value of an ARM Cortex-R5 core becoming undefined (represented as ‘X’) during wave simulation, while the same firmware runs correctly on an FPGA. This discrepancy suggests a simulation-specific problem rather than a fundamental hardware or firmware flaw. The…

ARM SVE2 Vector Length Limitations in Neoverse N1 FVP The Scalable Vector Extension 2 (SVE2) is a powerful feature in ARM architectures, designed to enhance performance for vectorized workloads. SVE2 supports vector lengths ranging from 128 bits to 2048 bits, allowing developers to write vector-length agnostic code. However, when working with Fixed Virtual Platforms (FVPs),…

ARM Cortex-R52 ATB Trace Data Mismatch During Instruction Execution The ARM Cortex-R52 processor, designed for real-time and safety-critical applications, provides extensive trace capabilities through the Advanced Trace Bus (ATB). The ATB is a critical component for debugging and performance analysis, as it captures instruction and data traces during program execution. However, discrepancies between the expected…

Understanding TCM Gate Unit in ARM Cortex-M85 Core The Tightly Coupled Memory (TCM) Gate Unit in the ARM Cortex-M85 core is a critical component that manages access to the TCM regions. TCM is a high-speed memory that is directly connected to the processor, providing low-latency access for time-critical code and data. The TCM Gate Unit…

ARM Cortex-A72 L1/L2 Cache ECC Disabling and Illegal Instruction Faults The ARM Cortex-A72 processor is a high-performance CPU core designed for applications requiring robust computational capabilities. One of its critical features is the inclusion of Error Correction Code (ECC) mechanisms for both Level 1 (L1) and Level 2 (L2) caches. ECC is a memory error…

ARMv8 Global Resource Access and VM Performance Bottlenecks In ARMv8 architectures, the majority of CPU registers are per-core, meaning each core in a multi-core processor has its own dedicated set of registers. However, certain resources, such as those managed by the Generic Interrupt Controller (GIC), are shared across multiple cores. These shared resources include global…