Author: System on Chips

PMU Event Counters Not Incrementing Despite Proper Configuration The Performance Monitoring Unit (PMU) in ARM Cortex-A72 processors is a powerful tool for profiling and analyzing system performance. However, a common issue arises when the event counters (PMXEVCNTR_EL0) remain at zero despite seemingly correct configuration and initialization. This problem is particularly perplexing because the cycle counter…

ARM Cortex-M33 WFI Behavior and UART4 Pending Interrupt Issue The STM32U599 microcontroller, based on the ARM Cortex-M33 core, is designed to provide low-power operation through the use of the WFI (Wait for Interrupt) instruction. The WFI instruction is a critical feature for power-sensitive applications, as it allows the CPU to enter a low-power state until…

ARM Cortex-M Stack Pointer Initialization Mechanism The ARM Cortex-M architecture employs a unique mechanism for initializing the Stack Pointer (SP) during the reset sequence. Unlike traditional processors where the stack pointer might be set explicitly by the first instruction in the reset handler, the Cortex-M series automatically loads the SP from the first entry of…

ARMv7-M Architecture Overview and Cortex-M3 Core Features The ARMv7-M architecture is a highly efficient, 32-bit RISC-based architecture designed for embedded systems, particularly those requiring real-time performance and low power consumption. It is part of the ARMv7 family, which includes three profiles: Application (A), Real-Time (R), and Microcontroller (M). The ARMv7-M profile is specifically tailored for…

ARM Chromebook Black Screen Due to nv-U-Boot SimpleFB and Kernel DTB Mismatch When upgrading the kernel and userland on an ARM-based Samsung Chromebook, a common issue arises where the screen turns black shortly after boot. This problem is often tied to the interaction between the nv-U-Boot firmware, specifically its SimpleFB implementation, and the kernel’s Device…

Understanding the Cortex-R5 Mode Switching Challenge The ARM Cortex-R5 processor, like many ARM cores, operates in multiple privilege modes to ensure secure and efficient execution of tasks. One common challenge developers face is transitioning between these modes, particularly from Supervisor mode (0x13) to System mode (0x1F). This transition is often required in embedded systems where…

GICv3 Interrupt Pending but Not Activating on i.MX8M Mini The issue at hand involves the ARM Cortex-A53-based i.MX8M Mini processor, where a General Purpose Timer 2 (GPT2) interrupt is generated but fails to transition from the pending state to the active state in the Generic Interrupt Controller (GIC). Specifically, the interrupt is correctly flagged as…

Cortex-A53 Cache Line Allocation Behavior and DC ZVA Instruction The Cortex-A53 processor, a popular choice in embedded systems and mobile devices, implements the ARMv8-A architecture. One of the key features of this architecture is the ability to manage cache lines efficiently, particularly through the use of the Data Cache Zero by Virtual Address (DC ZVA)…

ARM CHI Protocol and the Absence of Explicit Last Transaction Signals The ARM Coherent Hub Interface (CHI) protocol is a high-performance, scalable, and coherent interconnect protocol designed for modern ARM-based systems. Unlike the AXI protocol, which uses explicit signals like RLAST and WLAST to denote the last transaction in a burst, CHI employs a different…

EL2 to EL1 Transition Failure with Stack Usage in Bare-Metal Code The core issue revolves around a failure in transitioning from Exception Level 2 (EL2) to Exception Level 1 (EL1) on an ARM Cortex-A53 processor, specifically on a Raspberry Pi 3B. The EL2 code successfully initializes the UART and prints a message, but when it…