Author: System on Chips

ARM Cortex-M Reset Function Address Mismatch: VMA vs. LMA The issue at hand revolves around the discrepancy between the Virtual Memory Address (VMA) and the Load Memory Address (LMA) of the Reset function in an ARM Cortex-M microcontroller. Specifically, the Reset function is placed in the .text section of the ROM, with an LMA of…

ARMv8 Memory Barriers and Shareability Domains: The Core Issue In ARMv8 architectures, memory barriers (DMB) are critical for enforcing memory ordering guarantees across different processing elements (PEs) and shareability domains. The primary issue under discussion revolves around the practical differences between DMB NSHLD (Non-shareable Load Barrier) and DMB ISHLD (Inner Shareable Load Barrier). Specifically, the…

ARM Cortex-A9 Dual-Core AMP Mode Initialization Challenges The ARM Cortex-A9 dual-core processor is a popular choice for embedded systems requiring high performance and scalability. However, implementing Asymmetric Multiprocessing (AMP) mode on a baremetal system presents unique challenges, particularly when it comes to initializing the secondary core (CPU1) and ensuring proper synchronization between the two cores….

ARM Cortex-A55 TLB Coherency Issues During Context Switching with TTBR0 and TTBR1 In ARMv8-based systems, particularly those utilizing the Cortex-A55 processor, context switching between processes often involves managing Translation Lookaside Buffer (TLB) coherency when updating the Translation Table Base Registers (TTBR0 and TTBR1). The TLB is a critical component of the memory management unit (MMU)…

ARM Cortex-M7 Flash Access Performance Variability Due to Address Alignment The ARM Cortex-M7 processor, known for its high performance and efficiency, can exhibit significant variability in execution time for certain operations, particularly when accessing data from flash memory. This variability is especially pronounced when performing looped load-byte (LDRB) operations from flash memory to core registers….

ARM Cortex-A510 Dual-Core Complex VPU Sharing Mechanism The ARM Cortex-A510 processor, part of ARM’s latest generation of high-efficiency cores, introduces a dual-core complex architecture where two cores share a Vector Processing Unit (VPU). This design choice is aimed at optimizing silicon area and power efficiency, particularly in scenarios where both cores may not require simultaneous…

ARM Cortex-A53 NEON Intrinsics Misalignment and Cache Coherency Issues The issue described involves a "bus error" occurring when using the ARM NEON intrinsic vld2q_f32 on MediaTek MT676x series processors, specifically the MT6765 and MT6762. These processors are based on the ARM Cortex-A53 architecture, which implements the ARMv8-A instruction set. The vld2q_f32 intrinsic is designed to…

ARM Cortex-A55 L3 Cache Partitioning and Core-to-Partition Scheme ID Mapping The ARM Cortex-A55, as part of the DynamIQ Shared Unit (DSU), introduces a sophisticated mechanism for L3 cache partitioning. This partitioning is crucial for optimizing performance and resource allocation in multi-core systems. The L3 cache partitioning is managed through partition scheme IDs, which are assigned…

Cortex-R52 MCU Development: Missing CMSIS Support and Project Initialization Challenges The Cortex-R52 core, designed for real-time and safety-critical applications, presents unique challenges when establishing a new MCU engineering project. Developers often face difficulties in locating the appropriate CMSIS (Cortex Microcontroller Software Interface Standard) files, setting up a basic project in Eclipse, and compiling the project…

Cortex-A53 MMU Contiguous Bit Functionality at EL3 The Cortex-A53 Memory Management Unit (MMU) is a critical component in the ARMv8-A architecture, responsible for translating virtual addresses to physical addresses. One of the key features of the MMU is the contiguous bit in the block/page descriptor, which is used to optimize translation lookaside buffer (TLB) entries…