Author: System on Chips

Cortex-R5 L1 Cache Write-Streaming Mode and Cache Miss Anomalies The ARM Cortex-R5 processor is widely used in real-time embedded systems due to its deterministic performance and robust feature set. One of the key features of the Cortex-R5 is its L1 cache subsystem, which includes separate instruction and data caches. However, there is some ambiguity regarding…

Understanding Cortex-R52 CoreMark and DMIPS Performance Metrics The ARM Cortex-R52 is a high-performance real-time processor designed for safety-critical applications, offering features like dual-core lockstep, error correction, and advanced fault tolerance. Its performance is often measured using industry-standard benchmarks such as CoreMark and DMIPS (Dhrystone MIPS). CoreMark is a modern benchmark that evaluates the efficiency of…

Cortex-A15 Deadlock Due to Shared L2 Cache State in ACE Systems The Cortex-A15 processor, particularly in revision r2p4, is susceptible to a rare but critical deadlock condition when operating in an ACE (AXI Coherency Extensions) system. This deadlock arises under specific conditions involving shared L2 cache states, multiple caching masters, and the interplay between readUnique…

Understanding the Cortex-X4 Transistor Count and Physical Implementation The Cortex-X4, as part of Arm’s high-performance CPU lineup, is designed to deliver exceptional performance for advanced computing tasks. However, determining the exact transistor count or physical size of the Cortex-X4 core is not straightforward due to the nature of Arm’s business model and the flexibility it…

Determinism Challenges in ARM Multiprocessor Systems for DO-178C DAL A Compliance Determinism in embedded systems, particularly in safety-critical applications like avionics, is a non-negotiable requirement. The RTCA DO-178C Design Assurance Level A (DAL A) standard mandates that software must exhibit absolute determinism, meaning that execution times must be perfectly repeatable. This requirement becomes increasingly complex…

Understanding the ARM Cortex-M4 Floating-Point Unit (FPU) Presence The ARM Cortex-M4 processor is a widely used 32-bit RISC processor designed for embedded applications. One of its key features is the optional Floating-Point Unit (FPU), which accelerates floating-point arithmetic operations. However, not all Cortex-M4 implementations include an FPU, and its presence must be confirmed before leveraging…

Cortex-R82 MP Generation Failure in Socrates v1.7.0 The issue at hand revolves around the inability to generate a Cortex-R82 MP (Multi-Processor) configuration using the Socrates IP configuration tool version 1.7.0. Despite having the necessary IP bundle (MP130-BU-50000-r1p0-00lac0), the Cortex-R82 MP does not appear in the IP catalog list within Socrates. This prevents the user from…

Cortex-R52 Startup File Requirements and Challenges The Cortex-R52 is a high-performance, real-time processor designed for safety-critical applications, often used in automotive, industrial, and aerospace systems. Writing a startup file for the Cortex-R52 involves initializing the processor, setting up the memory map, configuring the stack pointers, and preparing the environment for the main application. Unlike the…

ARM Cortex-M33 ACI Implementation Challenges for 2D Convolution Optimization The Cortex-M33 processor, part of Arm’s Cortex-M series, is a powerful embedded processor designed for applications requiring a balance of performance, power efficiency, and security. One of its standout features is the support for Arm Custom Instructions (ACI), which allows silicon vendors to extend the processor’s…

Understanding the Difference Between Global System Counter and Cycle Counts The ARM Cortex-A53 processor, like many modern ARM cores, provides multiple mechanisms for tracking time and performance metrics. Two of the most commonly used mechanisms are the Global System Counter and the Performance Monitors Cycle Count Register (PMCCNTR_EL0). These two counters serve different purposes and…