Author: System on Chips

ARM DSU Performance Evaluation Challenges and Goals The DynamIQ Shared Unit (DSU) is a critical component in modern ARM-based systems, responsible for managing shared resources such as L2 and L3 caches, power management, and core coordination in multi-core ARM Cortex-A and Cortex-R processors. Evaluating the performance of the DSU is essential for system architects and…

Cortex-M7 DWT Watchpoint Configuration and Debug Event Issues The Cortex-M7 processor’s Data Watchpoint and Trace (DWT) unit is a powerful tool for debugging complex issues such as race conditions, memory corruption, and unexpected behavior in embedded systems. The DWT allows developers to set watchpoints on specific memory addresses, triggering debug events when those addresses are…

Cortex-M7 vs. Cortex-M3 FIR Filter Performance Discrepancy Overview The performance discrepancy between the Cortex-M7 and Cortex-M3 processors when executing a 128-tap FIR filter implementation has raised significant questions. The Cortex-M7, clocked at 600 MHz, demonstrates a runtime of 1260 microseconds for the FIR filter, while the Cortex-M3, clocked at 84 MHz, takes 44028 microseconds. This…

ETM FIFOFULL Overload in High-Speed Cortex-M7 and M4 Systems The Embedded Trace Macrocell (ETM) is a critical component for real-time debugging and performance analysis in ARM Cortex-M processors. However, in high-speed systems such as those utilizing Cortex-M7 cores running at 1GHz or Cortex-M4 cores at 400MHz, the ETM can become overwhelmed, leading to FIFOFULL events….

Cortex-A53 STL Accessibility for Independent Developers The ARM Cortex-A53 Safety Test Library (STL) is a critical resource for developers working on safety-critical applications, particularly in industries such as automotive, industrial automation, and medical devices. The STL provides a suite of tests designed to validate the functional safety of Cortex-A53-based systems, ensuring compliance with industry standards…

Cortex-R52+ Interrupt Latency: Key Factors and Realistic Benchmarks Interrupt latency is a critical performance metric in real-time embedded systems, particularly when using high-performance processors like the ARM Cortex-R52+. The Cortex-R52+ is designed for safety-critical applications, such as automotive and industrial systems, where deterministic and low-latency interrupt handling is paramount. Understanding the typical interrupt latency figures…

GICv3 Interrupt Priority Change Challenges with Pending Interrupts The ARM Generic Interrupt Controller (GIC) version 3 (GICv3) is a sophisticated interrupt management system designed to handle a wide range of interrupt scenarios in modern ARM-based systems. One of the more nuanced challenges when working with GICv3 is dynamically changing the priority of an interrupt that…

Cacheable and Shareable Attributes in ARM Cortex-R5F: A Deep Dive The ARM Cortex-R5F processor, based on the ARMv7 architecture, is widely used in real-time embedded systems due to its deterministic performance and efficient memory management capabilities. One of the critical aspects of memory management in ARM processors is the configuration of memory attributes, specifically the…

ARM Cortex-M85 ETM Data Trace Unsupported: Understanding the Limitation The ARM Cortex-M85 processor, a high-performance embedded processor designed for AI and machine learning applications, integrates the Arm CoreSight ETM-M85 (Embedded Trace Macrocell) for instruction tracing. However, a critical limitation arises when attempting to perform data tracing. The ETM-M85, as documented in the "Arm CoreSight ETM-M85…

Cortex-R52 Memory Map Flexibility and Design Philosophy The Cortex-R52 processor, unlike its Cortex-M series counterparts, does not come with a predefined default memory map. This design choice is intentional and stems from the need to provide system designers with maximum flexibility when integrating the Cortex-R52 into System-on-Chip (SoC) designs. The Cortex-R52 is often used in…