Author: System on Chips

Cortex-A53 DMIPS/MHz: Official Documentation and Unofficial Claims The Cortex-A53 is a highly efficient 64-bit ARM processor core designed for a wide range of applications, from mobile devices to embedded systems. One of the key metrics used to evaluate processor performance is DMIPS/MHz (Dhrystone MIPS per MHz), which provides a standardized measure of a processor’s integer…

Cortex-M55 Peripheral Access Configuration: AXI vs. AHB The Cortex-M55 processor, a member of Arm’s Cortex-M series, is designed for high-performance embedded applications, particularly those requiring machine learning and digital signal processing capabilities. One of its key architectural features is the ability to access peripherals using either the Advanced High-performance Bus (AHB) or the Advanced eXtensible…

ARM Cortex-M4F UDIV Instruction Timing Variability The ARM Cortex-M4F processor, a member of the Cortex-M series, is widely used in embedded systems due to its balance of performance and power efficiency. One of its key features is the inclusion of a hardware divide unit, which supports the UDIV (unsigned divide) instruction. Understanding the timing characteristics…

ARM64 LDR (Literal) Instruction and the VR Field in SIMD-FP Context The ARM64 instruction set architecture (ISA) is a rich and complex ecosystem designed to cater to a wide range of computational needs, from general-purpose processing to specialized tasks like Single Instruction Multiple Data (SIMD) and Floating-Point (FP) operations. One of the key instructions in…

Cortex-M Coprocessor Interface: Purpose and Limitations in Modern Embedded Systems The Cortex-M series of processors, widely used in embedded systems, includes a coprocessor interface designed to extend the functionality of the core processor. This interface allows for the integration of specialized hardware accelerators or additional processing units that can offload specific tasks from the main…

ARM Cortex-A78AE Core Halts During ERR0PFGCDN Register Configuration The ARM Cortex-A78AE core is designed with Reliability, Availability, and Serviceability (RAS) features to enhance fault tolerance and error handling in safety-critical applications. One of the key components of the RAS framework is the ability to inject faults for testing and validation purposes. However, during the configuration…

CPU Architecture: Hardware Foundations and Functional Design CPU architecture refers to the fundamental design and operational principles of a processor. It encompasses the hardware structure, including the data path, control units, memory hierarchy, and input/output mechanisms. In ARM systems, the CPU architecture defines how the processor executes instructions, manages memory, and handles exceptions. For instance,…

ARM Cortex-A53 Cache Contention and Memory Access Latency Variability The ARM Cortex-A53 is a widely used processor core in embedded systems, known for its balance of power efficiency and performance. However, when executing computationally intensive tasks across multiple cores, particularly those involving large memory arrays, users may encounter significant variability in execution times. This variability,…

ARM Cortex-M4 Register Corruption After WFI/Sleep Mode in FreeRTOS Issue Overview The core issue revolves around the corruption of the CPU register R7 after the Cortex-M4 processor exits sleep mode initiated by the WFI (Wait For Interrupt) instruction. This corruption manifests specifically during the first sleep cycle after system power-up, leading to an assertion failure…

ARM Cortex-A57 Hardware Prefetcher Behavior and Cache Benchmarking Challenges The ARM Cortex-A57 is a high-performance processor core designed for applications requiring significant computational power, such as mobile devices, networking equipment, and embedded systems. One of its key features is the inclusion of hardware prefetchers, which are designed to improve performance by predicting and preloading data…