Cortex-M55 Peripheral Access: Controlling AXI vs. AHB Interface

Cortex-M55 Peripheral Access Configuration: AXI vs. AHB

The Cortex-M55 processor, a member of Arm’s Cortex-M series, is designed for high-performance embedded applications, particularly those requiring machine learning and digital signal processing capabilities. One of its key architectural features is the ability to access peripherals using either the Advanced High-performance Bus (AHB) or the Advanced eXtensible Interface (AXI). This dual-bus architecture provides flexibility in system design but also introduces complexity in configuring the processor to use the desired bus for peripheral access. The issue at hand revolves around controlling whether the Cortex-M55 accesses peripherals via the AXI or AHB interface, specifically within the peripheral address range of 0x40000000 to 0x5FFFFFFF.

The Cortex-M55 Technical Reference Manual (TRM) states that data accesses in this range can be performed using either the Peripheral AHB (P-AHB) or the M-AXI interface. However, the manual does not provide explicit step-by-step guidance on how to configure the processor to prioritize one interface over the other. This lack of clarity can lead to confusion during system design, especially when performance optimization or specific bus protocol requirements are critical.

The primary mechanism for controlling this behavior lies in the P-AHB Control Register (PAHBCR) and the INITPAHBEN input signal. By manipulating these controls, developers can disable the P-AHB interface, forcing all peripheral accesses to occur over the M-AXI interface. Understanding how to configure these controls is essential for ensuring that the system operates as intended, particularly in scenarios where AXI’s higher bandwidth or advanced features are required.

PAHBCR.EN Bit and INITPAHBEN Signal: Key Control Mechanisms

The PAHBCR.EN bit and the INITPAHBEN input signal are the two primary mechanisms for controlling whether the Cortex-M55 uses the AHB or AXI interface for peripheral access. The PAHBCR.EN bit is a software-configurable register bit that enables or disables the P-AHB interface. When PAHBCR.EN is set to 1, the P-AHB interface is enabled, and peripheral accesses within the designated range are routed through the AHB bus. Conversely, when PAHBCR.EN is set to 0, the P-AHB interface is disabled, and all peripheral accesses are routed through the M-AXI interface.

The INITPAHBEN signal, on the other hand, is a hardware input signal that can override the PAHBCR.EN bit. This signal is typically used during system initialization to set the initial state of the P-AHB interface. If INITPAHBEN is asserted (set to 1) during reset, the P-AHB interface is enabled regardless of the PAHBCR.EN bit value. If INITPAHBEN is deasserted (set to 0) during reset, the P-AHB interface is disabled, and the M-AXI interface is used for peripheral access.

The relationship between the PAHBCR.EN bit and the INITPAHBEN signal is critical to understanding how the Cortex-M55 determines which bus to use. The INITPAHBEN signal takes precedence during the reset phase, ensuring that the system starts in a known state. After reset, the PAHBCR.EN bit can be modified to dynamically switch between the AHB and AXI interfaces as needed. This flexibility allows developers to optimize bus usage based on runtime requirements, such as switching to AXI for high-bandwidth data transfers or reverting to AHB for lower-latency access.

Configuring PAHBCR.EN and INITPAHBEN for AXI Peripheral Access

To ensure that the Cortex-M55 uses the AXI interface for peripheral access, developers must configure both the PAHBCR.EN bit and the INITPAHBEN signal appropriately. The following steps outline the process for achieving this configuration:

1. Initialization Phase: Setting INITPAHBEN
   During the hardware design phase, the INITPAHBEN signal must be connected to a logic level that reflects the desired initial state of the P-AHB interface. To disable the P-AHB interface and force AXI usage, INITPAHBEN should be tied to 0 (deasserted) in the system’s reset circuitry. This ensures that the P-AHB interface is disabled immediately after reset, routing all peripheral accesses through the M-AXI interface.

2. Software Configuration: Modifying PAHBCR.EN
   After the system exits the reset state, the PAHBCR.EN bit can be modified to maintain or change the bus configuration. To ensure that the M-AXI interface is used for peripheral access, the PAHBCR.EN bit must be set to 0. This can be achieved by writing to the PAHBCR register during system initialization. The following code snippet demonstrates how to disable the P-AHB interface in software:

   // Define the PAHBCR register address
   #define PAHBCR_ADDRESS 0xE000E000
   
   // Define the PAHBCR.EN bit position
   #define PAHBCR_EN_BIT 0
   
   // Disable the P-AHB interface by clearing the PAHBCR.EN bit
   *(volatile uint32_t *)(PAHBCR_ADDRESS) &= ~(1 << PAHBCR_EN_BIT);
   

   This code clears the PAHBCR.EN bit, ensuring that the P-AHB interface remains disabled and all peripheral accesses are routed through the M-AXI interface.

3. Verification and Debugging
   After configuring the PAHBCR.EN bit and INITPAHBEN signal, it is essential to verify that the Cortex-M55 is using the AXI interface as intended. This can be done by monitoring bus transactions using a debug probe or by analyzing system performance characteristics. If peripheral accesses are still routed through the AHB interface, developers should double-check the INITPAHBEN signal connection and ensure that the PAHBCR.EN bit is correctly cleared in software.

4. Handling Edge Cases
   In some systems, there may be scenarios where the P-AHB interface needs to be temporarily enabled for specific peripherals or operations. In such cases, the PAHBCR.EN bit can be dynamically toggled to switch between the AHB and AXI interfaces. However, developers must ensure that bus transitions do not introduce race conditions or undefined behavior. Proper synchronization mechanisms, such as memory barriers, should be used to guarantee consistent operation.

By following these steps, developers can effectively configure the Cortex-M55 to use the AXI interface for peripheral access, leveraging its advanced features and higher bandwidth for improved system performance. Understanding the interplay between the PAHBCR.EN bit and the INITPAHBEN signal is crucial for achieving the desired bus configuration and ensuring reliable operation in complex embedded systems.