ARM Cortex-M0+ DSM Integration Challenges in VCS Simulation The integration of ARM Cortex-M0+ Design Sign-off Models (DSMs) into a VCS simulation environment presents unique challenges, particularly when transitioning from Cadence to Synopsys toolchains. The core issue revolves around the proper configuration of Program Language Interface (PLI) commands in VCS to enable seamless interaction with the…
Cortex-M33 FVP Register Access Hard Fault Due to Memory Map Mismatch The issue at hand involves a hard fault occurring during register access while debugging a Cortex-M33-based firmware using the Fixed Virtual Platform (FVP). The firmware is developed for the LPCXpresso55S28 board, which features an NXP LPC55S28 microcontroller with a Cortex-M33 core. The hard fault…
ARM Cortex-M4 Cache Coherency Problems During DMA Transfers The issue described revolves around the Keil Pack Installer failing to update or download packs, specifically the STM32F3xx_DFP pack, and the subsequent absence of the STM family in the device database. This problem manifests in two primary ways: the Pack Installer displays a general error when attempting…
Direct AXI Stream Connection Between GIC-500 and Cortex-A53 When integrating ARM IPs such as the GIC-500 and Cortex-A53, the typical approach involves using an interconnect fabric to manage communication between the components. However, in some cases, designers may wish to establish a direct connection between these IPs without an intermediary interconnect. This scenario arises when…
PVBus Master Ports Not Generated in Simgen with AMBAPVACE Protocol When attempting to utilize the auto bridging feature in Simgen for the AMBAPVACE protocol, the PVBus master ports are not generated as expected. This issue arises specifically when configuring the master bridge for the PVBus protocol to use the PVBus2AMBAPVACE bridge in the JSON configuration…
Watchdog Timer Counts Down but HPS Fails to Reboot After Warm Reset The issue at hand involves the Cyclone V Hard Processor System (HPS) failing to reboot after a watchdog timer triggers a warm reset in a baremetal application. The watchdog timer is configured to count down and initiate a warm reset, but instead of…
ARM64 KVM Boot Failure on Fixed Virtual Platform (FVP) The core issue revolves around the inability to boot ARM64 KVM (Kernel-based Virtual Machine) on the ARM Fixed Virtual Platform (FVP). The user has successfully built a Linux-on-FVP environment but encounters issues when attempting to enable and verify KVM functionality. Despite ensuring that the KVM configuration…
ARM Cortex-A9 Instruction Set Compatibility Issue with "cpsie i" The error message "selected processor does not support cpsie i’ in ARM mode" indicates a fundamental incompatibility between the ARM Cortex-A9 processor in the Arria 10 SoC and the assembly instruction cpsie i. The cpsie i` instruction is used to enable interrupts by clearing the interrupt…
AMBA AHB Trace Macrocell (HTM) Compatibility with CoreSight SOC-400 The AMBA AHB Trace Macrocell (HTM) is a specialized component designed to trace transactions on the AMBA AHB bus, particularly for non-core masters such as DMA controllers. The HTM captures detailed information about AHB transactions, including address, data, and control signals, which is invaluable for debugging…
APB3 Slave PSLVERR Signal Optionality and Master Requirements The APB3 protocol, as defined in the ARM AMBA specification, is designed for low-power, low-complexity peripherals. One of the key features of APB3 is the introduction of the PSLVERR signal, which allows slaves to indicate error conditions during a transaction. However, the specification explicitly states that APB…