Author: System on Chips

VALID Before READY Handshake Rule in AXI Protocol The AXI protocol specifies a critical rule regarding the handshake process between the VALID and READY signals: a source is not permitted to wait for the READY signal to be asserted before asserting the VALID signal. This rule is fundamental to the proper operation of the AXI…

AXI3 WRAP Burst Address Alignment Requirements and Implications The AXI3 protocol specifies that WRAP burst transfers must use a start address that is aligned to the size of each transfer, as defined by the AxSIZE signal. This alignment requirement is critical for ensuring that the burst can correctly wrap around the boundary of the transfer…

NIC301 Write Transaction Behavior with 32-bit BusMatrix and 64-bit Slave The NIC301 interconnect is designed to handle data width conversion between masters and slaves with different data widths. In this scenario, the bus matrix operates at a 32-bit data width, while the slave interface is configured for a 64-bit data width. During write transactions, the…

AXI INCR Burst Transfer Mismatch Between 64-bit Data and 32-bit Bus When designing an ARM-based SoC, one common challenge is handling AXI INCR (Incrementing) burst transfers when the data width of the transaction does not match the bus width. In this case, the issue arises when a 64-bit data transaction needs to be transferred over…

AMBA AHB Lite Byte Addressing and Addressable Space Reduction The AMBA AHB Lite protocol is a widely used on-chip bus protocol in ARM-based SoC designs. One of its key features is its byte addressability, which allows for fine-grained memory access. However, this byte addressability introduces complexities when dealing with data transfers of less than the…

AXI Crossbar Address Decoding and DECERR Response Mechanism In ARM-based System-on-Chip (SoC) designs, the Advanced eXtensible Interface (AXI) protocol is widely used for high-performance communication between masters and slaves. One critical aspect of AXI-based systems is handling invalid address requests, which can occur when a master attempts to access an address that does not map…

WVALID Assertion Timing and Glitch During AXI Write Data Handshake The issue revolves around the assertion of the WVALID signal in the AXI (Advanced eXtensible Interface) write data channel during a handshake between the master and slave. Specifically, the problem occurs when the master attempts to assert WVALID in the same ACLK cycle where the…

AXI4 Unaligned Transfer Behavior with 32-bit Data on 64-bit Bus In AXI4-based systems, unaligned transfers occur when the starting address of a data transfer does not match the natural alignment boundary of the data width. For example, transferring 32-bit data on a 64-bit bus starting at address 0x001 is an unaligned transfer because the address…

WLAST Assertion Before WVALID and Address Issuance In AXI4-based designs, the timing of the WLAST signal relative to WVALID and the address phase (AW channel) can often lead to confusion, especially when observed in simulation waveforms. The WLAST signal is a critical component of the AXI4 write data channel (W channel), indicating the final transfer…

AXI4 Protocol Evolution: The Absence of WID The Advanced eXtensible Interface (AXI) protocol, developed by ARM, has undergone significant evolution from AXI3 to AXI4. One of the most notable changes in AXI4 is the removal of the Write ID (WID) signal, which was present in AXI3. The WID signal in AXI3 was used to support…