Cortex-A53 AXI Read Signal Anomalies with Non-Cacheable Memory The issue revolves around unexpected behavior in the AXI read signals when accessing non-cacheable memory regions on a Kria KV260 board with a Cortex-A53 processor. Specifically, the AXI read transactions exhibit discrepancies in signal values, such as ARSIZE and ARLEN, when compared to the expected behavior for…
ARMv8-A FVP SMMUv3 Device Integration and Request Simulation Challenges SMMUv3 Device Integration and Request Simulation in ARMv8-A FVP The integration of devices behind the System Memory Management Unit version 3 (SMMUv3) in an ARMv8-A Fixed Virtual Platform (FVP) presents a complex challenge, particularly when attempting to simulate device requests through the SMMUv3. The SMMUv3 is…
NIC-400 Reset Timing Challenges in Long-Distance SoC Implementations In complex System-on-Chip (SoC) designs utilizing ARM’s NIC-400 interconnect, one of the critical challenges is ensuring proper reset signal distribution across long physical distances. The NIC-400 interconnect, being a highly configurable network-on-chip (NoC) solution, often spans large sections of the SoC to connect multiple IP blocks, memory…
AWLEN Signal Optionality in AXI4 Masters and Its Implications for Slaves The AWLEN signal in the AXI4 protocol is a critical component of the write address channel, responsible for indicating the number of data transfers in a burst transaction. The AXI4 specification describes AWLEN as optional for masters but mandatory for slaves, which raises questions…
PL011 UART Interrupts Not Triggering in ARMv8-R AArch32 Mode When running Zephyr on an ARMv8-R AEM FVP in AArch32 mode, the PL011 UART interrupts are not being triggered. This issue can stem from multiple factors, including incorrect configuration of the PL011 UART peripheral, misalignment in the interrupt controller setup, or issues with the Zephyr OS…
ARM PL390 GIC Interrupt Priority Handling in Cyclone V SoC The ARM PL390 Generic Interrupt Controller (GIC) is a critical component in the Cyclone V SoC for managing interrupt priorities and ensuring that high-priority tasks are handled appropriately. The PL390 GIC is responsible for receiving interrupts from various sources, prioritizing them based on configured settings,…
AHB Lite Wrap Burst Calculation and Alignment Issues The AHB Lite protocol, a subset of the Advanced Microcontroller Bus Architecture (AMBA), is widely used in ARM-based SoC designs for its simplicity and efficiency in handling data transfers. One of the key features of AHB Lite is its support for burst transfers, which allow multiple data…
Dual Cortex-A9 Core Initialization and Synchronization Challenges When working with a dual-core ARM Cortex-A9 system like the CycloneV SoC, one of the primary challenges is ensuring proper initialization and synchronization between the two cores. The Cortex-A9 cores share a common L2 cache and are typically connected via an AXI coherency extension (ACE) interface, which allows…
AHB Slave HREADY Signal Behavior During Multi-Slave Transactions The AHB (Advanced High-performance Bus) protocol is a critical component of ARM’s AMBA (Advanced Microcontroller Bus Architecture) family, widely used in SoC designs for efficient communication between masters and slaves. One of the key signals in the AHB protocol is HREADY, which plays a dual role as…
ARM GPIO Fail-Safe, Retention, and Core Down Mode Functionality The ARM Artisan GPIO library provides three critical operational modes for GPIO pins: Fail-Safe, Retention, and Core Down. These modes are essential for ensuring robust and reliable operation in various power and fault scenarios. Understanding the functionality and application of these modes is crucial for designing…