AXI4 Master to AXI3 Slave Data Transfer Challenges with 64-bit to 32-bit Downsizing
When integrating an AXI4 master with an AXI3 slave in a System-on-Chip (SoC) design, one of the most common challenges arises from the mismatch in data widths and burst-length configurations. In this scenario, the AXI4 master is configured to send 64-bit data with a burst length of 1 (awlen = 1), while the AXI3 slave is designed to handle 32-bit data with the same burst length. This discrepancy can lead to protocol violations, data corruption, or even bus hangs if not properly addressed. The core issue revolves around how the AXI protocol handles data width conversion and burst-length alignment between different AXI versions.
The AXI protocol defines strict rules for burst transactions, including the alignment of addresses, the number of beats in a burst, and the handling of write strobes (wstrb). When a 64-bit AXI4 master communicates with a 32-bit AXI3 slave, the interconnect or bridge must downsample the data width from 64 bits to 32 bits. This process inherently converts a single 64-bit beat into two 32-bit beats. However, if the burst-length configurations (awlen) between the master and slave are not aligned, or if the address alignment rules are violated, the transaction can fail.
The primary symptoms of this issue include incomplete data transfers, incorrect data being written to the slave, or bus hangs. For example, if the AXI4 master sends a 64-bit data packet to an address that is not aligned to an 8-byte boundary, the slave may only receive part of the data or misinterpret the address, leading to incorrect data storage. Additionally, the write strobes (wstrb) must be correctly adjusted during the downsizing process to ensure that the correct bytes are written to the slave.
Misaligned Addresses and Burst-Length Mismatch as Root Causes
The root causes of these issues can be traced to two main factors: misaligned addresses and burst-length mismatches between the AXI4 master and AXI3 slave.
Misaligned Addresses
In AXI transactions, the address alignment is critical for ensuring that data is correctly mapped to the target memory or peripheral. The alignment requirement is determined by the data width and the burst type. For a 64-bit data width, the address must be aligned to an 8-byte boundary (i.e., the lower 3 bits of the address must be 000). If the address is not aligned, the transaction may span multiple address boundaries, leading to incorrect data being written or read.
For example, if the AXI4 master sends a 64-bit data packet to address 0x640_47CC, which is not aligned to an 8-byte boundary, the slave may interpret this as two separate 32-bit transactions at addresses 0x640_47CC and 0x640_47D0. However, if the slave expects the data to be aligned to a 4-byte boundary (as is typical for 32-bit data), it may only process the second 32-bit chunk, resulting in data loss or corruption.
Burst-Length Mismatch
The burst-length mismatch occurs when the AXI4 master and AXI3 slave have different expectations for the number of beats in a burst. In the AXI4 protocol, the burst length (awlen) is defined as the number of beats minus one. For example, a burst length of 1 (awlen = 1) indicates two beats. However, in the AXI3 protocol, the burst length is defined differently, and the interconnect must ensure that the burst-length values are correctly translated between the two protocols.
If the AXI4 master sends a burst with awlen = 1 (indicating two 64-bit beats), but the AXI3 slave interprets this as a single 32-bit beat, the transaction will fail. This is because the slave will only process one beat, leaving the second beat unhandled. This can lead to incomplete data transfers or bus hangs, as the master waits for a response that never arrives.
Write Strobe (wstrb) Handling
Another critical factor is the handling of write strobes (wstrb) during the downsizing process. The wstrb signal indicates which bytes of the data bus are valid for a write transaction. When downsizing from 64 bits to 32 bits, the wstrb must be adjusted to reflect the valid bytes in the 32-bit data bus. If this adjustment is not performed correctly, the slave may write incorrect data or fail to write data altogether.
For example, if the AXI4 master sends a 64-bit data packet with wstrb = 8'b1111_1111 (indicating all bytes are valid), the interconnect must split this into two 32-bit transactions with wstrb = 4'b1111 for each transaction. If the wstrb is not adjusted, the slave may only write part of the data, leading to data corruption.
Implementing Correct Data Width Conversion and Address Alignment
To resolve these issues, the following steps must be taken to ensure correct data width conversion, address alignment, and burst-length translation between the AXI4 master and AXI3 slave.
Data Width Conversion
The interconnect or bridge between the AXI4 master and AXI3 slave must correctly downsample the 64-bit data into two 32-bit transactions. This involves splitting the 64-bit data into two 32-bit chunks and sending them sequentially to the slave. The lower 32 bits of the data should be sent first, followed by the upper 32 bits. The wstrb signal must also be adjusted to reflect the valid bytes in each 32-bit transaction.
For example, if the AXI4 master sends a 64-bit data packet with wdata = 64'hCAFE_C8C8_A5A5_1F1F and wstrb = 8'b1111_1111, the interconnect should split this into two 32-bit transactions:
- First transaction:
wdata = 32'hA5A5_1F1F,wstrb = 4'b1111 - Second transaction:
wdata = 32'hCAFE_C8C8,wstrb = 4'b1111
Address Alignment
The AXI4 master must ensure that the address is aligned to an 8-byte boundary when sending 64-bit data. If the address is not aligned, the interconnect must handle the unaligned transaction by splitting it into multiple aligned transactions. For example, if the AXI4 master sends a 64-bit data packet to address 0x640_47CC, which is not aligned to an 8-byte boundary, the interconnect should split this into two transactions:
- First transaction: Address
0x640_47CC, 32-bit data0xXXXX_XXXX(partial data) - Second transaction: Address
0x640_47D0, 32-bit data0xXXXX_XXXX(remaining data)
Burst-Length Translation
The interconnect must correctly translate the burst-length values between the AXI4 master and AXI3 slave. If the AXI4 master sends a burst with awlen = 1 (indicating two 64-bit beats), the interconnect should convert this into a burst with awlen = 1 for the AXI3 slave (indicating two 32-bit beats). This ensures that the slave processes the correct number of beats and avoids burst-length violations.
Handling Unaligned Transfers
For unaligned transfers, the interconnect must ensure that the data is correctly split and reassembled. This involves generating additional transactions to handle the unaligned portions of the data. For example, if the AXI4 master sends a 64-bit data packet to address 0x640_47CC, the interconnect should generate the following transactions:
- First transaction: Address
0x640_47CC, 32-bit data0xXXXX_XXXX(partial data) - Second transaction: Address
0x640_47D0, 32-bit data0xXXXX_XXXX(remaining data)
The wstrb signal must also be adjusted to ensure that only the valid bytes are written to the slave. For example, if the first transaction only writes 2 bytes, the wstrb should be set to 4'b0011 to indicate that only the lower 2 bytes are valid.
Debugging and Verification
To verify the correctness of the implementation, the following steps should be taken:
- Use a simulation environment to model the AXI4 master, interconnect, and AXI3 slave.
- Generate test cases with different address alignments, burst lengths, and data patterns.
- Monitor the AXI signals (e.g.,
awaddr,wdata,wstrb,bready,bvalid) to ensure that the transactions are correctly handled. - Check the slave’s memory or registers to verify that the data is correctly written.
By following these steps, the issues related to burst-length violations, data width conversion, and address alignment can be effectively resolved, ensuring robust and reliable communication between the AXI4 master and AXI3 slave.
