BASEPRI and PRIGROUP Behavior in ARM Cortex-M33: Secure Hard Fault Analysis

ARM Cortex-M33 BASEPRI_NS Configuration and Secure Hard Fault

The ARM Cortex-M33 processor, like other Cortex-M series processors, utilizes a priority-based interrupt handling mechanism. This mechanism is governed by several key registers, including BASEPRI and PRIGROUP, which control the masking of interrupts based on their priority levels. In this scenario, the user is encountering a secure hard fault exception when executing an SVC instruction with BASEPRI_NS.BASEPRI[7:0] set to 1. The user’s understanding of the priority mechanism appears to be correct, but the occurrence of a secure hard fault suggests that there may be a deeper issue related to the interaction between the non-secure BASEPRI_NS register and the secure state of the processor.

The BASEPRI_NS register is used to mask interrupts with a priority lower than or equal to the value specified in BASEPRI_NS. In this case, BASEPRI_NS.BASEPRI[7:5] is set to 1, which should theoretically mask interrupts with a priority value of 1 or lower (numerically higher or equal). However, the SVCall interrupt, which has a default priority of 0, should not be masked because it has a higher priority than the BASEPRI_NS value of 1. The fact that a secure hard fault is occurring suggests that the SVCall interrupt is being treated as if it has a priority equal to or lower than the BASEPRI_NS value, which contradicts the expected behavior.

The PRIGROUP setting in the AIRCR register further complicates the priority mechanism. With PRIGROUP set to 0b000, the priority grouping is such that the group priority occupies bits [7:1], and the subpriority occupies bit [0]. Given that __NVIC_PRIO_BITS is 3, only bits [7:5] of the BASEPRI_NS register are valid, and the lower bits [4:0] are ignored. This configuration implies that all interrupts have a subpriority of 0, meaning that the configured interrupt priority is equivalent to the group priority.

Misconfiguration of BASEPRI_NS and Secure State Interaction

The primary issue here is the interaction between the non-secure BASEPRI_NS register and the secure state of the Cortex-M33 processor. The BASEPRI_NS register is intended to mask non-secure interrupts, but it should not affect secure interrupts. However, the occurrence of a secure hard fault suggests that the secure state is being influenced by the non-secure BASEPRI_NS setting. This could be due to several reasons:

1. Incorrect Configuration of Secure and Non-Secure States: The Cortex-M33 processor supports both secure and non-secure states, and the configuration of these states must be carefully managed. If the secure state is not properly configured, it may be incorrectly influenced by non-secure settings such as BASEPRI_NS.

2. Priority Inversion Due to PRIGROUP Setting: The PRIGROUP setting of 0b000 means that the group priority occupies bits [7:1], and the subpriority occupies bit [0]. However, with __NVIC_PRIO_BITS set to 3, only bits [7:5] are valid for the BASEPRI_NS register. This could lead to a situation where the secure interrupt priority is incorrectly interpreted, causing a priority inversion that results in a secure hard fault.

3. Misalignment Between BASEPRI_NS and SVCall Priority: The SVCall interrupt has a default priority of 0, which should be higher than the BASEPRI_NS value of 1. However, if there is a misalignment in how the priorities are being compared, the SVCall interrupt could be incorrectly masked, leading to a secure hard fault.

4. Hardware or Firmware Bug: There could be a bug in the hardware or firmware that is causing the secure hard fault. This could be related to how the BASEPRI_NS register is being handled in the secure state, or it could be a more general issue with the interrupt handling mechanism.

Resolving Secure Hard Faults by Correcting BASEPRI_NS and PRIGROUP Configuration

To resolve the secure hard fault issue, the following steps should be taken:

1. Verify Secure and Non-Secure State Configuration: Ensure that the secure and non-secure states are correctly configured. This includes checking the settings of the SAU (Security Attribution Unit) and the IDAU (Implementation Defined Attribution Unit) to ensure that the secure state is properly isolated from non-secure settings.

2. Re-evaluate PRIGROUP and BASEPRI_NS Settings: Re-examine the PRIGROUP and BASEPRI_NS settings to ensure that they are correctly aligned. Specifically, ensure that the BASEPRI_NS value is correctly interpreted given the PRIGROUP setting and the number of priority bits (__NVIC_PRIO_BITS).

3. Check SVCall Priority Configuration: Verify that the SVCall interrupt priority is correctly set to 0 and that it is not being incorrectly masked by the BASEPRI_NS register. This may involve checking the SHPR2.PRI_11 register to ensure that the SVCall priority is not being inadvertently modified.

4. Implement Debugging and Tracing: Use debugging tools such as the Tarmac trace or other ARM debugging tools to trace the execution flow and identify the exact point at which the secure hard fault occurs. This can provide valuable insights into the state of the processor and the registers at the time of the fault.

5. Review Firmware and Hardware for Bugs: If the issue persists, review the firmware and hardware for potential bugs. This may involve consulting the errata for the specific Cortex-M33 processor being used, as well as reviewing the firmware code for any potential issues related to interrupt handling.

6. Consult ARM Documentation and Support: If the issue cannot be resolved through the above steps, consult the ARM documentation and support resources for further guidance. ARM provides extensive documentation on the Cortex-M33 processor, including detailed information on interrupt handling and priority management.

By carefully following these steps, the secure hard fault issue can be resolved, ensuring that the BASEPRI_NS and PRIGROUP settings are correctly configured and that the secure state is properly isolated from non-secure settings. This will allow the Cortex-M33 processor to handle interrupts correctly, preventing the occurrence of secure hard faults and ensuring reliable operation of the system.

Detailed Analysis of BASEPRI_NS and PRIGROUP Interaction

To further understand the interaction between BASEPRI_NS and PRIGROUP, let’s delve into the details of how these registers work together to manage interrupt priorities.

BASEPRI_NS Register

The BASEPRI_NS register is used to mask interrupts with a priority lower than or equal to the value specified in the register. The value in BASEPRI_NS is compared to the priority of incoming interrupts, and if the interrupt priority is lower than or equal to the BASEPRI_NS value, the interrupt is masked. The BASEPRI_NS register is part of the non-secure state, meaning it should only affect non-secure interrupts.

PRIGROUP Setting

The PRIGROUP setting in the AIRCR register determines how the priority bits are divided between group priority and subpriority. With PRIGROUP set to 0b000, the group priority occupies bits [7:1], and the subpriority occupies bit [0]. This means that the group priority is the most significant part of the priority value, and the subpriority is the least significant part.

Priority Comparison

When an interrupt occurs, its priority is compared to the BASEPRI_NS value. The comparison is based on the group priority, as the subpriority is only used to resolve ties between interrupts with the same group priority. In this case, with PRIGROUP set to 0b000 and __NVIC_PRIO_BITS set to 3, only bits [7:5] of the BASEPRI_NS register are valid. This means that the effective BASEPRI_NS value is determined by bits [7:5], and the lower bits [4:0] are ignored.

Secure Hard Fault Analysis

Given the above understanding, the secure hard fault occurring when BASEPRI_NS.BASEPRI[7:5] is set to 1 suggests that the SVCall interrupt, which has a default priority of 0, is being incorrectly masked. This could be due to a misalignment in how the priorities are being compared. Specifically, if the secure state is incorrectly interpreting the BASEPRI_NS value, it may be treating the SVCall interrupt as if it has a priority equal to or lower than the BASEPRI_NS value, leading to a secure hard fault.

Correcting the Configuration

To correct this issue, the following steps should be taken:

1. Ensure Proper Secure State Configuration: Verify that the secure state is correctly configured and isolated from non-secure settings. This includes checking the SAU and IDAU settings to ensure that secure interrupts are not being influenced by non-secure settings such as BASEPRI_NS.

2. Re-evaluate PRIGROUP and BASEPRI_NS Settings: Re-examine the PRIGROUP and BASEPRI_NS settings to ensure that they are correctly aligned. Specifically, ensure that the BASEPRI_NS value is correctly interpreted given the PRIGROUP setting and the number of priority bits (__NVIC_PRIO_BITS).

3. Check SVCall Priority Configuration: Verify that the SVCall interrupt priority is correctly set to 0 and that it is not being incorrectly masked by the BASEPRI_NS register. This may involve checking the SHPR2.PRI_11 register to ensure that the SVCall priority is not being inadvertently modified.

4. Implement Debugging and Tracing: Use debugging tools such as the Tarmac trace or other ARM debugging tools to trace the execution flow and identify the exact point at which the secure hard fault occurs. This can provide valuable insights into the state of the processor and the registers at the time of the fault.

5. Review Firmware and Hardware for Bugs: If the issue persists, review the firmware and hardware for potential bugs. This may involve consulting the errata for the specific Cortex-M33 processor being used, as well as reviewing the firmware code for any potential issues related to interrupt handling.

6. Consult ARM Documentation and Support: If the issue cannot be resolved through the above steps, consult the ARM documentation and support resources for further guidance. ARM provides extensive documentation on the Cortex-M33 processor, including detailed information on interrupt handling and priority management.

By carefully following these steps, the secure hard fault issue can be resolved, ensuring that the BASEPRI_NS and PRIGROUP settings are correctly configured and that the secure state is properly isolated from non-secure settings. This will allow the Cortex-M33 processor to handle interrupts correctly, preventing the occurrence of secure hard faults and ensuring reliable operation of the system.

Conclusion

The interaction between BASEPRI_NS and PRIGROUP in the ARM Cortex-M33 processor is a complex but crucial aspect of interrupt handling. Misconfigurations in these settings can lead to unexpected behavior, such as secure hard faults, which can be challenging to diagnose and resolve. By understanding the underlying mechanisms and carefully configuring the secure and non-secure states, it is possible to prevent these issues and ensure the reliable operation of the system. The steps outlined in this guide provide a comprehensive approach to troubleshooting and resolving secure hard faults related to BASEPRI_NS and PRIGROUP settings in the ARM Cortex-M33 processor.