SMMU-v3 Memory Attribute Configuration and Coherency Challenges The System Memory Management Unit version 3 (SMMU-v3) is a critical component in modern ARM-based systems, enabling virtualization and memory protection for I/O devices. However, configuring memory attributes and ensuring coherency between the CPU and SMMU can be challenging, especially when dealing with non-coherent memory accesses. This post…
Cortex-A72 Cache Internal Memory Access Mechanism The Cortex-A72 processor, part of ARM’s Cortex-A series, is a high-performance CPU designed for advanced applications requiring significant computational power. One of the critical features of the Cortex-A72 is its cache architecture, which includes Level 1 (L1) instruction and data caches, as well as a unified Level 2 (L2)…
ARM Cortex-A Secure and Non-Secure Address Space Interactions In ARM architectures, particularly those implementing TrustZone technology, the distinction between Secure and Non-Secure worlds is fundamental to system security. The ARM Cortex-A series processors, which often utilize the AXI (Advanced eXtensible Interface) protocol, are designed to handle transactions between these two worlds with strict separation. When…
Understanding the AA64nAA32 Signal and Boot Execution State The LS1027A SoC, featuring dual ARM Cortex-A72 cores, is a powerful processor often used in embedded systems requiring high performance. One critical aspect of its operation is determining the execution state (AArch32 or AArch64) during the boot process. This determination is governed by the AA64nAA32 signal, which…
ARM Cortex-M Flash Memory Protection Mechanisms The ARM Cortex-M series of microcontrollers is widely used in embedded systems due to its efficiency, low power consumption, and robust performance. However, one critical aspect that developers must address is the security of the firmware stored in the microcontroller’s flash memory. Unauthorized access to this firmware can lead…
ARM Cortex-M4 Exclusive and Locked Access Scenarios Issue Overview In ARM architectures, exclusive and locked access mechanisms are critical for ensuring atomic operations in multi-master systems. Atomic operations are sequences of read-modify-write operations that must complete without interruption to maintain data integrity. Exclusive access and locked access are two distinct methods used to achieve atomicity,…
ARM Cortex-M4 Usage Fault Due to Missing Coprocessor Support The ARM Cortex-M4 processor is a widely used embedded microcontroller core that combines high performance with low power consumption. However, one of the challenges developers face when working with the Cortex-M4 is ensuring compatibility with software that may rely on coprocessor instructions. In this case, the…
ARM Cortex-A53 System Counter and Kernel Boot Timing Discrepancy The issue revolves around a significant discrepancy between the kernel boot timestamps reported by the ARM Cortex-A53-based Rockchip RK3568 board and the actual boot time measured using an external device (iPhone). The kernel reports a boot time of 10 seconds via dmesg, while the actual boot…
Persistent Data Storage Requirements for Password Management in Cortex-M4 When designing a system that requires persistent data storage, such as password management in an embedded system based on the ARM Cortex-M4 processor, several key considerations must be addressed. The primary requirement is to ensure that data remains intact even after the device is disconnected from…
ARM Cortex-A53 Cache Coherency Issues Between EL1 and EL3 in Shared Memory Regions Cache Coherency Challenges in Multi-Exception Level Systems In systems utilizing ARM Cortex-A53 processors, cache coherency between different Exception Levels (ELs) can present significant challenges, particularly when shared memory regions are involved. The Cortex-A53, being a part of the ARMv8-A architecture, supports multiple…