ARM Cortex-A53 Exception Return CPSR Corruption During EL3 to EL1 Transition
ARM Cortex-A53 CPSR Corruption After Exception Return from EL3 to EL1 The ARM Cortex-A53 processor, part of the ARMv8-A architecture, is designed to handle exceptions and interrupts across multiple exception levels (ELs). A critical issue arises when returning from an exception in EL3 (Secure Monitor) to EL1 (OS Kernel), where the CPSR (Current Program Status…