Cortex-M1 Softcore Processor Application Project Generation Failure in Vitis 2020.1
The core issue revolves around the failure to generate an application project in Vitis 2020.1 for a Cortex-M1 softcore processor implemented on an Arty A7 100T FPGA. The user successfully generated a bitstream for a simple AXI-Uartlite project using Vivado 2020.1 and exported the hardware XSA (Xilinx Support Archive) file. However, when attempting to create a basic C/C++ application project in Vitis 2020.1 using the exported XSA file, the platform creation succeeds, but the application project generation fails with the error message "Failed to call GENERATE_APP." The Vitis log file indicates that the hsi::generate_app command failed due to earlier errors, leading to a cascade of exceptions during the project creation process.
The error manifests during the application project creation phase, specifically when Vitis attempts to generate the application template using the XSCT (Xilinx Software Command-line Tool) server. The log reveals that the XSCT server starts successfully, and the platform repository initializes without issues. However, the generate_app command fails, resulting in a java.lang.RuntimeException and subsequent errors in the module responsible for updating project references. This suggests that the failure is not due to a platform creation issue but rather a problem with the application template generation or the underlying project configuration.
The Cortex-M1 softcore processor is a configurable IP core designed for FPGA implementations, and its integration with the Arty A7 100T FPGA involves several layers of toolchain interactions, including Vivado for hardware design, Vitis for software development, and XSCT for command-line operations. The failure to generate the application project indicates a potential misconfiguration or compatibility issue within the Vitis environment, the XSA file, or the Cortex-M1 processor setup.
XSA File Misconfiguration and Toolchain Compatibility Issues
One of the primary causes of the application project generation failure is a misconfiguration in the exported XSA file. The XSA file contains metadata about the hardware design, including the processor configuration, peripheral interfaces, and memory maps. If the XSA file does not accurately reflect the Cortex-M1 processor’s configuration or if it contains inconsistencies, Vitis may fail to generate the application project. For example, if the memory map specified in the XSA file does not match the actual hardware design, the generate_app command may encounter errors when attempting to create the application template.
Another potential cause is toolchain compatibility issues. Vitis 2020.1 is a specific version of the Xilinx toolchain, and it may have known bugs or limitations when working with certain processor configurations or FPGA boards. The Cortex-M1 softcore processor, while supported by Xilinx, may require specific settings or patches to function correctly with Vitis 2020.1. Additionally, the Arty A7 100T FPGA board may have unique requirements or constraints that are not fully accounted for in the default Vitis project templates.
The XSCT server’s role in the application project generation process also introduces potential points of failure. The XSCT server is responsible for executing commands such as getProjects and getPlatforms, which retrieve information about the available projects and platforms in the workspace. If the XSCT server encounters errors during these operations, it may fail to properly initialize the application project, leading to the observed GENERATE_APP failure. The log indicates that the XSCT server successfully retrieves project and platform information, but the subsequent generate_app command fails, suggesting that the issue lies in the application template generation rather than the platform initialization.
Resolving XSA File Issues and Ensuring Toolchain Compatibility
To troubleshoot and resolve the application project generation failure, the first step is to verify the integrity and configuration of the exported XSA file. This involves opening the XSA file in Vivado and ensuring that all hardware components, including the Cortex-M1 processor, are correctly configured and that the memory map aligns with the design specifications. Any discrepancies should be corrected, and the XSA file should be re-exported from Vivado. It is also advisable to check for any warnings or errors during the XSA file export process, as these may indicate underlying issues that could affect the application project generation.
Next, ensure that the Vitis 2020.1 toolchain is properly configured to support the Cortex-M1 softcore processor and the Arty A7 100T FPGA. This includes verifying that the correct board support package (BSP) is installed and that any necessary patches or updates for Vitis 2020.1 are applied. The Xilinx support website and forums are valuable resources for identifying known issues and obtaining the latest updates for the toolchain. If compatibility issues persist, consider testing the design with a different version of Vitis or consulting Xilinx support for guidance.
The XSCT server’s behavior during the application project generation process should also be examined. The log indicates that the XSCT server successfully starts and retrieves project and platform information, but the generate_app command fails. To diagnose this issue, manually execute the generate_app command using the XSCT command-line interface. This allows for more detailed error messages and insights into the root cause of the failure. If the manual execution of the generate_app command reveals specific errors, these can be addressed by modifying the application template or adjusting the project settings in Vitis.
If the above steps do not resolve the issue, consider creating a minimal example project that replicates the problem. This involves creating a new Vivado project with only the Cortex-M1 processor and the necessary peripherals, exporting the XSA file, and attempting to generate the application project in Vitis. By isolating the issue to a minimal example, it becomes easier to identify and address the root cause. Additionally, sharing the minimal example project with the Xilinx community or support team can facilitate further assistance and troubleshooting.
In summary, the failure to generate an application project in Vitis 2020.1 for a Cortex-M1 softcore processor on an Arty A7 100T FPGA is likely due to a combination of XSA file misconfiguration and toolchain compatibility issues. By verifying the XSA file, ensuring toolchain compatibility, and diagnosing the XSCT server’s behavior, the issue can be resolved, enabling successful application project generation and further development on the Cortex-M1 platform.
