ARM Cortex-A Core Handling of Group 1 Interrupts in EL3 with GICv3
The ARM Cortex-A series processors, when operating at Exception Level 3 (EL3), present a unique scenario for handling Group 1 interrupts, particularly when interfacing with the Generic Interrupt Controller version 3 (GICv3). The core of the issue revolves around the behavior of the ICC_EOIR1_EL1 register, which is responsible for performing priority drops for Group 1 interrupts. The confusion arises from the interpretation of the GICv3 architecture specification, which delineates the handling of Secure and Non-secure Group 1 interrupts differently based on the processor’s current state (Secure or Non-secure) and the Exception Level (EL).
The GICv3 architecture specification states that a write to ICC_EOIR1_EL1 performs a priority drop for Non-secure Group 1 interrupts if the Processing Element (PE) is operating in a Non-secure state or at EL3. Conversely, when operating in a Secure state, a write to ICC_EOIR1_EL1 performs a priority drop for Secure Group 1 interrupts. This dual behavior raises questions about whether EL3, which is inherently a Secure Exception Level, can handle both Secure and Non-secure Group 1 interrupts or if it is limited to Non-secure interrupts only.
The pseudo-code provided in the GICv3 specification (section 13.1.3) clarifies this behavior. It indicates that when the highest priority active interrupt is a Non-secure Group 1 (G1NS) interrupt, the priority is dropped if the CPU is at EL3 or in a Non-secure state. Similarly, when the interrupt is a Secure Group 1 (G1S) interrupt, the priority is dropped if the CPU is in a Secure state, which includes EL3. This implies that EL3 can indeed handle both Secure and Non-secure Group 1 interrupts, provided that the interrupts are routed to EL3.
Secure State Interpretation and EL3 Interrupt Routing
The interpretation of the Secure state in the context of EL3 is crucial for understanding the handling of Group 1 interrupts. The ARMv8 architecture defines the Secure state as encompassing EL3 along with the Secure levels below EL3 (EL2 and EL1). This means that when the processor is operating at EL3, it is considered to be in a Secure state, and thus, it can handle Secure Group 1 interrupts by writing to ICC_EOIR1_EL1.
However, the ability to handle Non-secure Group 1 interrupts at EL3 is contingent upon the interrupt routing configuration. The ARMv8 manual (section D1.13.1) details the routing of asynchronous exceptions under various configuration options. Specifically, it outlines how interrupts can be routed to different Exception Levels based on the security state and the configuration of the GICv3. For EL3 to handle Non-secure Group 1 interrupts, the interrupt must be explicitly routed to EL3, which is typically controlled by the GICv3’s interrupt routing registers.
The pseudo-code from the GICv3 specification further elucidates this by showing that the IsEL3OrMon() function returns true when the processor is at EL3, allowing the priority drop for Non-secure Group 1 interrupts. This is in addition to the IsSecure() function, which returns true for EL3, enabling the priority drop for Secure Group 1 interrupts. Therefore, EL3 can handle both types of interrupts, but the routing configuration must be correctly set up to ensure that the interrupts are directed to EL3.
Implementing Priority Drop for Group 1 Interrupts in EL3
To implement the priority drop for Group 1 interrupts in EL3, several steps must be followed to ensure that the interrupts are correctly handled and that the priority drop is performed as expected. The first step is to configure the GICv3 to route the desired interrupts to EL3. This involves setting the appropriate bits in the GICv3’s interrupt routing registers, such as the ICC_IGRPEN1_EL1 and ICC_IGRPEN0_EL1 registers, which control the enabling of Group 1 and Group 0 interrupts, respectively.
Once the interrupts are routed to EL3, the next step is to handle the interrupt in the EL3 exception handler. When an interrupt is received at EL3, the handler must determine whether the interrupt is a Secure or Non-secure Group 1 interrupt. This can be done by examining the interrupt ID and the corresponding GICv3 registers, such as the ICC_IAR1_EL1 register, which provides the interrupt ID and the group information.
After identifying the interrupt type, the handler must perform the priority drop by writing to the ICC_EOIR1_EL1 register. The value written to this register should be the interrupt ID obtained from the ICC_IAR1_EL1 register. This write operation will trigger the priority drop for the corresponding interrupt, allowing the processor to resume normal operation.
It is important to note that the priority drop operation must be performed in the correct order to avoid race conditions and ensure that the interrupt handling is atomic. The ARMv8 architecture provides memory synchronization instructions, such as Data Synchronization Barriers (DSB), to ensure that the write to ICC_EOIR1_EL1 is completed before the processor proceeds with further operations.
In summary, handling Group 1 interrupts in EL3 with GICv3 requires a thorough understanding of the ARMv8 architecture and the GICv3 specification. The key steps include configuring the GICv3 to route interrupts to EL3, identifying the interrupt type in the EL3 exception handler, and performing the priority drop by writing to the ICC_EOIR1_EL1 register. By following these steps, developers can ensure that both Secure and Non-secure Group 1 interrupts are correctly handled at EL3, providing a robust and secure interrupt handling mechanism for ARM Cortex-A processors.
