The Cortex-M4 processor handles exceptions and interrupts using vector numbers. A vector number is assigned to each type of exception and allows the processor to quickly branch to the specific exception handler when an exception occurs. The vector numbers are useful for configuring the processor’s Nested Vectored Interrupt Controller (NVIC) and for writing exception handler functions.
Reset
The first vector number is for the reset exception. This exception occurs when the processor is reset and allows the processor to initialize and start executing code. The reset vector number is:
- Vector #1: Reset
NMI
The Non-Maskable Interrupt (NMI) exception cannot be disabled by software. It is used for critical events like memory faults. The NMI vector number is:
- Vector #2: Non-Maskable Interrupt (NMI)
HardFault
The HardFault exception handles fatal errors during exception processing. It indicates there is a defect in the program or its environment. The HardFault vector number is:
- Vector #3: HardFault
MemManage
The MemManage exception occurs on memory protection faults, such as invalid memory access permissions. It is used if memory protection features are enabled. The MemManage vector number is:
- Vector #4: MemManage
BusFault
The BusFault exception occurs on bus errors, such as invalid instruction fetches. It allows the processor to recover from bus faults. The BusFault vector number is:
- Vector #5: BusFault
UsageFault
The UsageFault exception occurs on faults related to instruction execution, such as invalid instructions and illegal unaligned accesses. It assists debugging. The UsageFault vector number is:
- Vector #6: UsageFault
SecureFault
The SecureFault exception supports Armv8-M Security Extensions. It occurs on secure faults when in the non-secure state. The SecureFault vector number is:
- Vector #7: SecureFault
SVCall
The SVCall exception is triggered by the SVC instruction. It allows switching to privileged mode for OS kernel functions. The SVC vector number is:
- Vector #11: SVCall
PendSV
The PendSV exception allows low priority interrupts to be handled. PendSV is triggered by software to force a context switch. The PendSV vector number is:
- Vector #14: PendSV
SysTick
The SysTick exception handles the system tick timer. It allows real-time task management. The SysTick vector number is:
- Vector #15: SysTick
External Interrupts
The external interrupt vectors allow external hardware to generate interrupts. Up to 240 external interrupt vectors can be configured, numbered #16 to #255. For example:
- Vector #16: External Interrupt 0
- Vector #17: External Interrupt 1
- …
- Vector #255: External Interrupt 239
Configuring NVIC Vector Priorities
The NVIC allows configuring priorities for the exception vectors. Higher priority vectors can preempt lower priority ones. The NVIC priorities do not correspond directly to vector numbers.
For example, Reset could have low priority while a time-critical external interrupt has high priority. The NVIC priority levels are numbered 0 (highest) to 255 (lowest). So Reset could have priority 200 while the time-critical interrupt has priority 0.
Usage in Software
Knowing the Cortex-M4 exception vector numbers allows properly configuring NVIC priorities and writing exception handler functions.
For example, an external interrupt handler would be written as:
void External_Interrupt_Handler(void) {
// Handle interrupt
}
And in the startup code, the interrupt vector would be configured:
void External_Interrupt_Config(void) {
// Set priority level
NVIC_SetPriority(External_Interrupt, Priority_Level);
// Enable interrupt
NVIC_EnableIRQ(External_Interrupt);
}
The vector number maps to the specific interrupt. This allows the correct handler to be called based on the exception vector number.
For system exceptions, the handlers can provide useful debugging information. For example, the HardFault handler may output the fault status registers to help identify the source of the fault:
void HardFault_Handler(void) {
__asm("TST LR, #4");
__asm("ITE EQ");
__asm("MRSEQ R0, MSP");
__asm("MRSNE R0, PSP");
__asm("B print_fault_status");
}
void print_fault_status(uint32_t* hardfault_args) {
// Print stacked fault status registers
// to debug exception
}
Listing All Vector Numbers
For easy reference, here is a compact list of all the Cortex-M4 exception vector numbers and their associated exceptions:
- #1 Reset
- #2 NMI
- #3 HardFault
- #4 MemManage
- #5 BusFault
- #6 UsageFault
- #7 SecureFault
- #8 Reserved
- #9 Reserved
- #10 Reserved
- #11 SVCall
- #12 Reserved
- #13 Reserved
- #14 PendSV
- #15 SysTick
- #16+ External Interrupt IRQ0
- #17+ External Interrupt IRQ1
- …
- #255 External Interrupt IRQ239
Conclusion
In summary, the Cortex-M4 processor handles exceptions and interrupts using vector numbers from #1 to #255. Knowing the meaning behind these vectors helps configure interrupt priorities, write correct exception handlers, and debug processor faults. The vectors allow quick branching to specific exception handlers in response to external interrupts or internal processor exceptions. Overall, the vector numbers provide an important map between exception sources and their associated handler functions.