ARM Cortex-A78 Cache Performance Metrics: L3D_CACHE_REFILL and LL_CACHE_MISS_RD
L3D_CACHE_REFILL and LL_CACHE_MISS_RD Event Definitions and Discrepancies
In the ARM Cortex-A78 architecture, cache performance metrics are critical for understanding system behavior, particularly in high-performance computing environments. Two key metrics, L3D_CACHE_REFILL and LL_CACHE_MISS_RD, often cause confusion due to their seemingly overlapping definitions but differing behaviors in practice.
The L3D_CACHE_REFILL event counts the number of times the L3 data cache experiences a refill, which occurs when a cache miss happens at the L3 level, and data must be fetched from main memory or another cache level. This event is directly tied to the L3 cache’s operation and is a measure of how often the L3 cache fails to satisfy a data request, necessitating a refill from a slower memory source.
On the other hand, the LL_CACHE_MISS_RD event, as described in the Cortex-A78 Technical Reference Manual (TRM), counts last-level cache misses for read transactions. The behavior of this event depends on the configuration of the CPUECTLR.EXTLLC bit. When CPUECTLR.EXTLLC is set to 0, LL_CACHE_MISS_RD is supposed to be a duplicate of the L3D_CACHE_REFILL_RD event, meaning it should count the same events as L3D_CACHE_REFILL. However, in practice, these two events often show different counts, leading to confusion and misinterpretation of cache performance data.
The discrepancy between L3D_CACHE_REFILL and LL_CACHE_MISS_RD can be attributed to several factors, including the specific implementation details of the Cortex-A78, the configuration of the cache hierarchy, and the exact conditions under which these events are counted. Understanding these factors is crucial for accurate performance profiling and optimization.
Configuration and Implementation Details Affecting Cache Event Counts
The Cortex-A78’s cache hierarchy and configuration play a significant role in how cache events are counted. The CPUECTLR.EXTLLC bit, in particular, is a critical factor. When CPUECTLR.EXTLLC is set to 0, the LL_CACHE_MISS_RD event is expected to mirror the L3D_CACHE_REFILL event, as both should count last-level cache misses. However, the actual behavior can differ due to several reasons.
First, the L3D_CACHE_REFILL event is specifically tied to the L3 data cache, counting only those misses that result in a refill from main memory or another cache level. In contrast, LL_CACHE_MISS_RD may include additional conditions or filters that affect its counting. For example, LL_CACHE_MISS_RD might only count misses that result in data being fetched from DRAM, while L3D_CACHE_REFILL could include misses that are satisfied by other cache levels within the same cluster.
Second, the Cortex-A78’s cache hierarchy includes multiple levels of cache, including per-core L1 and L2 caches, and a shared L3 cache. The interaction between these cache levels can lead to complex behaviors that are not immediately apparent from the TRM descriptions. For instance, a read transaction that misses in the L1 and L2 caches but hits in the L3 cache would not be counted by L3D_CACHE_REFILL, but might still be counted by LL_CACHE_MISS_RD if it meets certain criteria.
Third, the Cortex-A78’s implementation of cache coherency and memory ordering can also affect how cache events are counted. The architecture includes various mechanisms for maintaining cache coherency across multiple cores and clusters, and these mechanisms can influence the behavior of cache events. For example, a cache miss that triggers a coherency operation might be counted differently by L3D_CACHE_REFILL and LL_CACHE_MISS_RD.
Accurate Cache Performance Profiling: Choosing the Right Metric
When profiling cache performance on the Cortex-A78, it is essential to choose the right metric based on the specific aspect of cache behavior you wish to analyze. If the goal is to understand the frequency of L3 cache refills, L3D_CACHE_REFILL is the appropriate metric. This event provides a direct measure of how often the L3 cache fails to satisfy a data request, necessitating a refill from a slower memory source.
On the other hand, if the goal is to understand last-level cache misses for read transactions, LL_CACHE_MISS_RD might be more appropriate, but with caution. Given the potential discrepancies between LL_CACHE_MISS_RD and L3D_CACHE_REFILL, it is important to carefully consider the configuration and implementation details of the Cortex-A78 when interpreting the results. In some cases, it may be necessary to use both metrics in conjunction to get a complete picture of cache performance.
To ensure accurate profiling, it is also important to consider the specific workload and system configuration. Different workloads can exhibit different cache behaviors, and the configuration of the cache hierarchy can significantly impact the results. For example, a workload that generates a high number of cache misses might show different patterns of L3D_CACHE_REFILL and LL_CACHE_MISS_RD events depending on the size and associativity of the L3 cache.
In conclusion, while L3D_CACHE_REFILL and LL_CACHE_MISS_RD are both valuable metrics for understanding cache performance on the Cortex-A78, they are not interchangeable. Careful consideration of the architecture’s configuration and implementation details is necessary to accurately interpret these metrics and make informed decisions about performance optimization. By understanding the nuances of these events, developers can better diagnose and address cache-related performance bottlenecks in their systems.
