Author: Graham Kruk

The ARM Floating Point Unit (FPU) provides hardware support for calculations using floating point numbers. The FPU instruction set allows ARM processors to perform mathematical operations efficiently on single precision and double precision floating point values. Overview of ARM FPU The ARM FPU is an optional extension to the ARM instruction set architecture. It provides

The ARM Cortex-M0 is a 32-bit reduced instruction set computing (RISC) processor designed for microcontroller applications. It is one of the simplest and smallest processors in the Cortex-M series, aimed at low-cost and low-power embedded systems. The Cortex-M0 clock speed determines how fast instructions are executed and ultimately limits the performance of the microcontroller. Cortex-M0

The ARM application binary interface (ABI) defines the low-level interface between an application and the ARM processor architecture. It determines how functions are called between an application and the operating system as well as how data is passed between the two. Understanding the ARM ABI is crucial for developing applications that are compatible and optimized

ARM CPUs can be broadly divided into three profiles – Application profile, Real-time profile and Microcontroller profile. The Application profile is meant for high performance application processors like those used in smartphones. The Real-time profile is for real-time embedded systems that need deterministic timing behavior. The Microcontroller profile covers the microcontroller market and aims to

Assembly language is a low-level programming language that directly corresponds to a computer’s underlying machine or assembly language. Unlike high-level languages like C/C++, assembly language consists of mnemonic codes that directly control a microprocessor’s components like registers, arithmetic logic unit, etc. Learning assembly language allows programmers to write optimized code by directly controlling the CPU’s

The ARM Cortex-M3 is a 32-bit RISC processor core licensed by ARM Holdings. It is intended for microcontroller use, and has been implemented by many chip manufacturers in their microcontroller products. The Cortex-M3 processor has a 3-stage pipeline and uses the ARMv7-M architecture, which includes Thumb-2 technology for improved code density. This allows it to

The STM32F407 is an ARM Cortex-M4 core-based high-performance microcontroller developed by STMicroelectronics. It offers advanced processing capabilities, high-speed connectivity, and rich peripherals while maintaining low power consumption. Overview The STM32F407 is based on the high-performance ARM Cortex-M4 32-bit RISC core which can run up to 168MHz. It has 1MB of flash memory and 192KB of

The ARM Cortex-M Exception Program Status Register (EPSR) is a key register that controls exception and interrupt handling in Cortex-M processors. It indicates the current processor state and tracks exception-related information to assist with exception entry and exit. Understanding the EPSR is crucial for developers working with Cortex-M devices. Overview of the EPSR The EPSR

The xPSR (program status register) is one of the key registers in the ARM Cortex-M3 processor. It contains information about the current state of the processor and is used to control and monitor program execution. Overview of xPSR The xPSR is a 32-bit read/write register that combines bits from the following CPU status registers: The

The ARM trap instruction allows developers to trigger exceptions intentionally in ARM-based systems. It provides a mechanism to switch from unprivileged mode to privileged mode in order to run exception handlers or operating system code. The trap instruction is an important part of implementing protected operating systems and hypervisors on ARM processors. What is the