Author: Graham Kruk

Basepri is a register found in ARM Cortex processor cores that controls the priority level of exception handlers. It plays a key role in determining the priority of different exceptions and interrupts in the ARM architecture. In a nutshell, Basepri allows software to dynamically raise the priority of exception handlers to prevent lower priority exceptions

The ARM Cortex M3 is primarily considered a microcontroller, which contains elements of both a processor and peripheral interfaces and controllers. However, the Cortex M3 blurs the line between a traditional microcontroller and a standalone processor. Key Characteristics of the Cortex M3 The Cortex M3 has several key features that give it both processor and

ARM Cortex-M processors have multiple modes to provide different levels of access and functionality. The main modes are Thread Mode, Handler Mode, and Privileged Mode. Understanding these modes and when the processor switches between them is key to developing robust and secure embedded systems. Thread Mode Thread Mode is where the Cortex-M processor spends most

Bare metal code refers to programs that run directly on the hardware, without the support of an operating system. It is considered a type of low-level programming, as it requires directly interfacing with and controlling the underlying hardware components. However, the term “low level” itself can have different meanings in software development. In general, low-level

Bare metal embedded programming refers to developing firmware directly on microcontroller hardware, without relying on any operating system (OS). The programmer writes all the low-level code to directly interface with the processor and peripherals. This provides precise control over the hardware but requires in-depth knowledge of the specific microcontroller architecture. Key Characteristics of Bare Metal

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm Holdings. The cores are intended for microcontroller use, and consist of the Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M55 and Cortex-M65. The ARM Cortex-M processors are designed for embedded applications requiring high performance and low power consumption.

The Arm Cortex startup sequence refers to the steps that are followed when powering up an Arm Cortex-based system-on-chip (SoC). This startup process initializes the processor, memory, and peripherals to get the system into an operational state. The exact details of the startup sequence can vary between different Arm Cortex implementations and SoC designs, but

The boot process of a microcontroller refers to the sequence of events that take place when the microcontroller is first powered on or reset. This process loads the initial program code into memory and prepares the microcontroller for operation. The key steps in the typical boot process of a microcontroller are: Power On Reset When

The ARM Cortex series refers to ARM processor cores designed by Arm Holdings for use in a variety of devices including microcontrollers. However, the ARM Cortex cores themselves are not standalone microcontrollers. Rather, they are CPU cores that get incorporated into system-on-a-chip (SoC) designs by semiconductor companies to make complete microcontroller units. So in summary,

The Cortex-M0 is a 32-bit ARM processor core designed for microcontroller applications. It is one of the smallest and simplest cores in the Cortex-M series, optimized for low-cost and low-power embedded systems. The Cortex-M0 uses the Thumb-2 instruction set, which is a mix of 16-bit and 32-bit instructions. The 16-bit Thumb instructions provide high code