Author: Mike Johnston

Context switching is the process where the processor switches from one thread to another. This involves storing the state of the current thread and loading the state of the next thread to be executed. While context switching is essential for multitasking, it can sometimes lead to hard faults that crash the system if not handled

The Cortex-M1 processor from ARM is a 32-bit RISC processor optimized for microcontroller applications. It supports advanced interrupt handling and configurable prioritized exception handling to meet real-time system requirements. Proper configuration of interrupts and exceptions is critical for developing robust and responsive Cortex-M1-based systems. Cortex-M1 Interrupt Architecture The Cortex-M1 processor provides extensive support for fast,

The Arm Cortex-M1 processor is designed for low-power embedded applications. It has a simple memory system without caches or memory management units. The Cortex-M1 memory system needs to be configured correctly for optimal performance and power efficiency. Cortex-M1 Memory Architecture The Cortex-M1 contains separate instruction and data bus interfaces to external memory. It has a

The key difference in exception handling between Cortex-M and Cortex-R processors is that Cortex-M uses the Nested Vectored Interrupt Controller (NVIC) while Cortex-R uses the Generic Interrupt Controller (GIC). The NVIC allows for tailored exception handling with a priority-based preemption model, while the GIC is more flexible and supports up to 1020 interrupt sources. Cortex-M

The main differences between the Arm Cortex-M1 and Cortex-R4 processors are that the Cortex-M1 is an older, 32-bit microcontroller focused on low cost and power efficiency, while the Cortex-R4 is a newer, more powerful 32-bit real-time processor aimed at more demanding embedded applications. The Cortex-M1 has a simpler architecture and instruction set compared to the

The ARM Cortex-M0 and Cortex-M0+ processors based on the ARMv6-M architecture are highly optimized for energy efficiency and low cost. However, the GNU toolchain (GNU compiler collection + GNU binutils) often generates inefficient code for these microcontrollers, leading to poor performance. This article provides workarounds and optimizations to get the most out of your ARMv6-M

Adding a hardware multiplier unit and MULH instruction to the Cortex-M0+ can significantly improve performance for applications that perform many multiplications on 16-bit values. While software multiplication is possible on the Cortex-M0+, it is much slower than using a hardware multiplier. The MULH instruction allows retrieving the upper 16 bits of a 32-bit multiply result,

The Cortex M0+ microcontroller from ARM is well-suited for audio decoding applications in USB memory sticks due to its low power consumption, small size, and built-in DSP capabilities. By leveraging the Cortex M0+ processor, USB drive manufacturers can add high-quality audio playback to standard thumb drives without significantly increasing cost or power draw. Overview of

When using external BRAM with the Cortex-M1 processor, it is important to properly configure the reset behavior to ensure correct system operation. The Cortex-M1 supports flexible reset configurations to accommodate different use cases. This article provides guidance on configuring the start-up reset behavior when integrating external BRAM with Cortex-M1. Overview of Cortex-M1 Reset The Cortex-M1

The Cortex-M1 processor from ARM can be debugged using a JTAG (Joint Test Action Group) debugger. JTAG provides a standard way to connect debugging tools to the processor and gain visibility into the running code. A JTAG debugger is an invaluable tool for firmware engineers working with Cortex-M1 as it allows stepping through code, setting