Author: Neil Salmon

The Cortex-M0 is one of ARM’s most basic and widespread microcontroller cores. As an ultra low power 32-bit chip optimized for cost-sensitive and power-constrained embedded applications, Cortex-M0 can be found in a vast range of IoT and wearable devices. To develop software for Cortex-M0, understanding how to build the correct startup code and initialization routines

The Cortex-M0 processor supports a debug mode called Cycle Mode or Data Streaming Mode (DSM) that allows real-time data to be streamed off-chip while the processor continues to execute instructions. This is useful for debugging and profiling applications by observing the processor’s state without halting execution. Enabling DSM mode is done by setting the DSM

Cortex-M0+ processors utilize the Thumb-1 instruction set which is optimized for code density rather than performance. While compact code size is advantageous for microcontrollers with limited memory, it can result in suboptimal execution speed. By reorganizing C code in certain ways, we can optimize it to make better use of the Thumb-1 instruction set and

The Cortex-M0+ is an ultra low power 32-bit ARM processor designed for embedded and IoT applications. During development, users may encounter an error when trying to program or “flash” new firmware onto the chip, commonly referred to as the “Flash Download failed” error. There are several potential causes for this error, which we will explore

The short answer is yes, the GCC compiler is capable of detecting some unaligned accesses during compilation for Cortex-M0 and other ARM Cortex-M processors. However, the level of unaligned access detection during compilation depends on the specific compiler version and optimization flags used. In general, newer versions of GCC have improved unaligned access detection. And

The Cortex-M0 is the smallest and most energy-efficient processor in the Cortex-M series of ARM processors. As an ultra low power microcontroller, the Cortex-M0 is designed for resource constrained devices and applications where cost and power consumption are critical factors. One of the ways the Cortex-M0 achieves its low power consumption is by having a

Flash memory programming is essential for working with microcontrollers like the Cortex M0 that utilize on-chip flash memory for storing firmware. Understanding the basic concepts of flash memory and the process of programming it enables developers to efficiently write, deploy and update firmware on Cortex M0 chips. Overview of Flash Memory Flash memory is a

The ARM Cortex-M0 is one of the smallest and lowest power microcontrollers in the Cortex-M series. With its limited flash memory and RAM, optimizing code and data size is critical for Cortex-M0 designs. This article provides an overview of techniques to reduce code and RAM usage when developing applications for the Cortex-M0. Overview of Cortex-M0

Yes, it is possible to program FPGA Block RAM connected to a Cortex-M0 processor using JTAG. JTAG provides a standard way to debug and program embedded systems and can be used to write data to Block RAM inside an FPGA fabric from an external JTAG host. Here is an overview of how it can be

The Cortex-M0+ is an ultra-low power 32-bit ARM Cortex-M processor optimized for cost-sensitive and power-constrained embedded applications. One of its key features is the embedded flash memory or EEPROM that allows you to store and retrieve information even when the power is turned off. Copying data to the EEPROM with Cortex M0+ can be useful