Author: Neil Salmon

The “SWD-Port of the Cortex-M0: Cannot connect to MEM-AP on Cortex-M0 Designstart Eval” error indicates an issue with connecting to the memory access port (MEM-AP) when trying to debug or program a Cortex-M0 microcontroller over the Serial Wire Debug (SWD) interface. This is commonly seen when using development boards like the DesignStart Eval board with

When an interrupt occurs on a Cortex M0 processor, the processor must handle the interrupt properly by saving its current state, servicing the interrupt handler routine, and then restoring its previous state upon return from the interrupt. This process allows the processor to temporarily pause what it was doing, take care of the urgent interrupt

The Cortex-M0 is an ultra low power 32-bit ARM processor core designed for microcontroller applications. It is optimized for low cost and low power embedded systems. To aid in development and debugging of Cortex-M0 based systems, ARM provides a debug interface and viewer software. The debug viewer allows developers to view the processor state, memory,

The Cortex-M0+ processor from Arm is an ultra low power 32-bit RISC CPU core designed for microcontroller applications. It builds on the success of the earlier Cortex-M0 core by adding new features like dual-issue pipeline, configurable memory protection unit, and higher energy efficiency while maintaining full code compatibility with Cortex-M0. One key aspect of Cortex-M0+

Cortex-M0+ microcontrollers (MCUs) from ARM offer a good balance of performance, power efficiency, and cost for a wide range of embedded applications. While there are some common features across Cortex-M0+ chips, there can also be significant differences between models from different manufacturers. Overall, Cortex-M0+ strikes a compromise between customization and generalization. Common Features of Cortex-M0+

When a hard fault occurs on Cortex-M0+, it is critical to be able to print out the call stack to debug what went wrong. This can be achieved by implementing a hard fault handler that leverages the stack frame to output the call stack. Here is a step-by-step guide on how to do this on

The Cortex-M0+ processor from ARM is an extremely popular 32-bit microcontroller that is used in a wide range of embedded systems. As with any microcontroller, robust fault handling is essential for stable operation. One common issue that can occur with Cortex-M0+ devices is problems with the hard fault handler. The hard fault handler in Cortex-M0+

The ARM Cortex-M0 is an ultra low power 32-bit ARM processor core designed for microcontrollers and deeply embedded applications. It features a reduced instruction set computing (RISC) architecture and a flexible interrupt controller for rapid response to real-time events. The PGA970 is a specific implementation of the Cortex-M0 core by NXP Semiconductors. A common need

Multiplying two 32-bit numbers to get a 64-bit result is a common operation in many embedded and IoT applications running on Cortex M0/M0+ chips. The default 32×32->64-bit multiplication opcode provided by ARM takes 32 clock cycles to complete, which can be slow for time-critical code. This article discusses techniques to significantly speed up 32-bit multiplication

Setting a section’s attributes using the Memory Protection Unit (MPU) can affect the CPU’s ordering of that specific section. The MPU allows configuring access permissions and cache policies for different memory regions. Setting strict ordering for a section via the MPU results in the CPU forcing transactions to that section to occur in program order.