Author: System on Chips

Custom SoC vs. Discrete STM32L562: Balancing Parallel Development Tracks When transitioning from a discrete microcontroller-based design, such as the STM32L562, to a custom System-on-Chip (SoC), one of the most critical challenges is managing parallel development tracks. The STM32L562 is a low-power ARM Cortex-M33-based microcontroller, widely used in embedded systems for its balance of performance, power…

ARM Cortex-M Exclusive Access Branch Out of Range Error The issue at hand revolves around an assembly code snippet provided in the CoreSight Components Technical Reference Manual (ARM DDI 0314H) on page 310. The code is intended to demonstrate how to perform an exclusive write to the stimulus port of an ARM Cortex-M processor. However,…

ARM Cortex-M7 Atomic Operation Faults on Non-Cacheable Memory Issue Overview: LDREX Bus Faults in Non-Cacheable Memory Regions The ARM Cortex-M7 processor is a high-performance microcontroller core designed for real-time and embedded applications. One of its key features is the Memory Protection Unit (MPU), which allows developers to define memory regions with specific attributes such as…

4×4 Matrix Keypad Scanning Mechanism and Common Implementation Issues The integration of a 4×4 matrix keypad with an ARM microcontroller involves a scanning mechanism that allows the microcontroller to detect key presses efficiently. The keypad consists of 16 buttons arranged in a 4-row by 4-column matrix. Each row and column is connected to a GPIO…

Cortex-A53 L2 Cache Invalidation Mechanism The Cortex-A53 processor, part of ARM’s Cortex-A series, is a widely used 64-bit ARMv8-A core that features a multi-level cache hierarchy, including L1 and L2 caches. The L1 cache is split into instruction (L1 I-cache) and data (L1 D-cache) caches, while the L2 cache is typically unified, meaning it stores…

ARM Cortex-M4 Interrupt Handling Flow and ICPR Register Role The ARM Cortex-M4 processor employs a sophisticated interrupt handling mechanism managed by the Nested Vectored Interrupt Controller (NVIC). The NVIC is responsible for prioritizing and managing interrupts, ensuring that the processor can handle multiple interrupt sources efficiently. At the heart of this mechanism are two key…

ARM Cortex-M0+ NOP Cycle Time and Interrupt Latency Anomalies The ARM Cortex-M0+ is a highly efficient and widely used microcontroller core, known for its simplicity and low power consumption. However, when operating at a clock frequency of 40MHz, the expected cycle time for a NOP instruction should be 25ns. Instead, measurements indicate a cycle time…

ARMv8 DIC/IDC Bits and Their Role in Cache Coherency The ARMv8 architecture introduces two critical bits in the Cache Type Register (CTR_EL0): DIC (Data Independent Timing) and IDC (Instruction Independent Timing). These bits play a pivotal role in managing cache coherency between the Data Cache (DCache) and the Instruction Cache (ICache). The primary function of…

Understanding AXI4 Narrow and Unaligned Read Transactions The AXI4 protocol is a widely used interface standard for high-performance embedded systems, particularly in ARM-based designs. One of the more nuanced aspects of AXI4 is handling narrow and unaligned read transactions. Narrow transactions refer to data transfers where the data width is less than the full width…

ARM Cortex-A53 and Cortex-A35 Architectural Differences and Boot Code Implications The ARM Cortex-A53 and Cortex-A35 are both 64-bit ARMv8-A processors, but they are designed for different performance and power efficiency targets. The Cortex-A53 is part of ARM’s "big.LITTLE" architecture, often used in high-performance applications, while the Cortex-A35 is optimized for ultra-low power consumption and is…