Author: System on Chips

ARM Cortex-A65 Power Test Measurement Windows and Missing LD1 Instruction in saxpy_simd The ARM Cortex-A65 processor incorporates power test measurement windows to evaluate power consumption under specific workloads, such as maxpwr_cpu, maxpwr_cpu_int, maxpwr_l2, and saxpy_simd. These tests are designed to measure peak power consumption in different operational scenarios, including CPU-intensive tasks, L2 cache activity, and…

ARM AXI5 Protocol Requirements for Write and Read Transactions The ARM AXI5 protocol, as defined in the AMBA® AXI Protocol Specification (IHI0022K, A3.4), imposes specific requirements on how managers (masters) handle write and read transactions. These requirements are designed to ensure efficient and predictable data flow within the system, minimizing latency and avoiding deadlocks. The…

APB Bus Protocol and the Necessity of PENABLE Signal The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family, designed for low-bandwidth control accesses to peripherals. It is a simple, non-pipelined protocol that is easy to implement and is typically used for connecting low-speed peripherals to the system bus….

ARM Cortex-R52 Fast Models Incorrectly Writing Zeroes to Flash for BSS Section The issue revolves around the ARM Cortex-R52 Fast Models incorrectly handling the BSS (Block Started by Symbol) section of an ELF file during simulation. The BSS section, which is marked as NOLOAD in the ELF file, is intended to reserve space in RAM…

AXI Write Strobe Signals and Their Impact on Read-Modify-Write Operations The AXI (Advanced eXtensible Interface) protocol is a widely used on-chip communication standard for high-performance embedded systems. One of its key features is the ability to perform efficient data transfers using write strobe signals (WSTRB). These signals determine which byte lanes of the data bus…

AMBA5 Bus Matrix Address Remapping and Alias Behavior in SIE-200 The AMBA5 Bus Matrix, particularly in the context of the ARM SIE-200 IP, introduces a sophisticated mechanism for address remapping and aliasing, which can be both powerful and complex. This post delves into the intricacies of how address remapping and aliasing work within the Bus…

AXI4 Protocol Behavior During Write Address and Data Transfers The AXI4 protocol is designed to handle multiple outstanding transactions, ensuring that write addresses and corresponding data are processed in a specific order. When a master initiates a write transaction, the address is sent on the AW channel, and the data is sent on the W…

AXI5 Data-less Write Transactions and Their Protocol Requirements The AXI5 protocol, as defined in the ARM IHI 0022 Issue K specification, introduces the concept of data-less write transactions. These transactions are unique in that they do not involve the transfer of data on the WDATA channel, yet they still require a formalized sequence of events…

AXI4 Aligned Address Calculation for INCR Bursts In AXI4, the concept of an aligned address is crucial for understanding how address generation works during INCR (incrementing) burst transactions. An aligned address ensures that each subsequent transfer in a burst adheres to the alignment requirements specified by the AxSIZE signal. The AxSIZE signal defines the number…

ARM CHI ReadUnique Final State: UC vs. UD and Cache Coherency Implications The ARM Coherent Hub Interface (CHI) protocol is a critical component of modern ARM-based systems, enabling efficient cache coherency and data sharing across multiple request nodes (RNs) and home nodes (HNs). One of the key transactions in the CHI protocol is the ReadUnique…