Author: System on Chips

AHB5 Narrow Burst Write Transfers and Strobe Calculation Challenges The Advanced High-performance Bus (AHB) protocol, particularly AHB5, is widely used in ARM-based systems for high-speed data transfers between masters and slaves. One of the critical aspects of AHB5 is the generation and interpretation of write strobes (HWSTRB) during narrow burst transfers, where the transfer size…

GIC-500 Initialization and Configuration Complexity in Bare-Metal Systems The integration of the ARM Cortex-A35 processor with the Generic Interrupt Controller 500 (GIC-500) in a bare-metal environment presents several challenges, particularly in the initialization and configuration of the GIC-500. The GIC-500 is a critical component in managing interrupts for multi-core systems, and its proper setup is…

HTRANS Behavior During AHB Error Response Cycles The Advanced High-performance Bus (AHB) protocol is a critical component of ARM-based systems, governing how data transfers occur between masters and slaves. One of the key signals in the AHB protocol is HTRANS, which indicates the type of transfer being performed. The HTRANS signal can take on several…

ARMv8 Translation Fault Level 0 During TTBR0_EL1 Switch from Identity Mapping to User Process The core issue revolves around a translation fault level 0 occurring after switching the TTBR0_EL1 register from an identity mapping to a user process mapping in an ARMv8-based system, specifically on a Raspberry Pi 4B (BCM2711). The fault manifests when attempting…

ARM Cortex-M0 vs. Cortex-M4 Performance and Instruction Set Challenges The BBC Micro:bit v1 and v2 present a unique challenge due to their vastly different hardware architectures. The v1 is powered by a Nordic nRF51822 microcontroller featuring a 16 MHz ARM Cortex-M0 core, while the v2 utilizes a Nordic nRF52833 with a 64 MHz ARM Cortex-M4…

ARMv8 MMU Translation Fault with 4KiB Granules in TTBR0_EL1 The ARMv8 architecture provides a sophisticated Memory Management Unit (MMU) that supports multiple translation table formats, including 4KiB, 16KiB, and 64KiB granule sizes. However, when configuring the MMU for user-space mappings using TTBR0_EL1, a common issue arises when attempting to use 4KiB blocks, resulting in a…

ARM Cortex-A Core Handling of Group 1 Interrupts in EL3 with GICv3 The ARM Cortex-A series processors, when operating at Exception Level 3 (EL3), present a unique scenario for handling Group 1 interrupts, particularly when interfacing with the Generic Interrupt Controller version 3 (GICv3). The core of the issue revolves around the behavior of the…

ARM Cortex-M0/3/4 Toolchain Generating Mixed Thumb-16 and Thumb-32 Instructions The ARM Cortex-M series of processors, including the Cortex-M0, Cortex-M3, and Cortex-M4, are designed to execute Thumb instructions, which are a compact form of ARM instructions. Thumb instructions come in two variants: Thumb-16 and Thumb-32. Thumb-16 instructions are 16 bits wide, offering higher code density, while…

ARM Cortex-A72 Core Frequency Locking for Functional Evaluation When evaluating specific functions or performance characteristics on an ARM Cortex-A72 core, it is often necessary to lock the core frequency to a predefined value. This ensures consistent and repeatable results, especially when analyzing performance bottlenecks, power consumption, or thermal behavior. However, the ARM Cortex-A72, like many…

Understanding the Missing Stack Section in Cortex-A72 Linker Files When working with baremetal applications on ARM Cortex-A72 processors, one of the critical tasks is setting up the stack in the linker file. The stack is essential for function calls, local variable storage, and interrupt handling. However, a common issue arises when the .stack section defined…