Author: System on Chips

ARM CHI ReadShared with Exclusive Access and ReadUnique: Key Differences and Use Cases The ARM Coherent Hub Interface (CHI) specification defines a set of protocols and transactions for managing coherence and data transfers in multi-core systems. Among these transactions, ReadShared with Exclusive Access and ReadUnique are two critical operations that serve distinct purposes in managing…

AXI4 Protocol Write Interleaving Removal and Its Impact on Bus Throughput The AXI4 protocol, a cornerstone of modern ARM-based systems, explicitly removed support for write interleaving, a feature present in its predecessor, AXI3. Write interleaving allowed multiple write transactions from different masters to be interleaved at the data phase, enabling higher bus utilization in scenarios…

APU Core Crashes During 32-bit Mode Boot Process The issue involves an ARM Processing Unit (APU) with four cores (Core 0 to Core 3) executing a Built-In Test (BIT) in 64-bit mode during the Secondary Stage Boot Loader (SSBL) phase. Upon completion of the BIT, cores 1 to 3 are placed into a power-on reset…

ARM Cortex-A53 Dual-Core Synchronization Exceptions with Shared Page Tables In a dual-core ARM Cortex-A53 system, sharing page tables between cores is a common practice to simplify memory management and reduce overhead. However, this approach can lead to synchronization exceptions if the implementation is not carefully handled. This post delves into the root causes of such…

Cortex-A35 Feature Configuration and ATF Initialization Challenges The ARM Cortex-A35 is a highly efficient processor designed for power-sensitive applications, offering a balance between performance and energy efficiency. However, its flexibility in feature configuration can sometimes lead to unexpected behavior during system initialization, particularly when working with the ARM Trusted Firmware (ATF). The ATF is responsible…

Ethos-U55 MAC and Elementwise Engine Concurrency Challenges The Ethos-U55 Neural Processing Unit (NPU) is a highly optimized accelerator designed for machine learning workloads, featuring specialized engines such as the Multiply-Accumulate (MAC) Engine and the Elementwise Engine. These engines are designed to handle specific types of operations efficiently. However, a critical question arises regarding their ability…

EL3 to Non-Secure EL1 Transition Failure and Missing EL1 Entry Call When transitioning from EL3 (Exception Level 3) to non-secure EL1 (Exception Level 1) on an ARM Cortex-A55 processor, the CPU successfully switches to EL1h (non-secure mode), but the el1_entry function is never called. This issue is particularly perplexing because the same code works when…

CoreSight Device Enumeration Failure on Nvidia Jetson Nano and AGX Xavier The CoreSight debugging and tracing infrastructure is a critical component for developers working on ARM-based systems, enabling real-time tracing, profiling, and debugging of complex software and hardware interactions. However, when attempting to use CoreSight on Nvidia Jetson platforms such as the Jetson Nano and…

ARM Cortex-R52+ Floating-Point Register Corruption During Interrupt Handling The ARM Cortex-R52+ is a high-performance real-time processor designed for safety-critical applications. One of its key features is the support for floating-point operations, which are essential for tasks requiring precision calculations. However, in certain scenarios, particularly when dealing with interrupts and context switching, floating-point register corruption can…

Cortex-A78 and ArmRAL: Understanding the Compatibility and Performance Implications The Cortex-A78, a high-performance processor based on the ARMv8.2-A architecture, is widely used in applications requiring significant computational power, such as SmartNICs. ArmRAL (Arm RAN Acceleration Library) is a critical tool for accelerating 5G NR signal processing workloads, leveraging vector engines like Neon, SVE, and SVE2….