Author: System on Chips

ARM Cortex-A53 Double Precision Floating-Point Printout Anomaly The issue at hand involves the incorrect printout of a double-precision floating-point value on an ARM Cortex-A53 core. Specifically, when printing a negative double value using the %e format specifier, the Cortex-A53 incorrectly outputs the value as positive, whereas the same code running on an ARM Cortex-M4 core…

ARM Cortex-M7 PWM Signal Generation Capabilities and Constraints The ARM Cortex-M7 core, as found in the STM32F7xx and STM32H7xx microcontrollers, is a high-performance processor designed for real-time applications. One of its key features is the ability to generate Pulse Width Modulation (PWM) signals, which are essential for controlling motors, LEDs, and other devices that require…

ARM Cortex-A53 STUR Instruction and Synchronous Exception Overview The ARM Cortex-A53 processor, operating in AArch64 mode, is a widely used 64-bit ARM core known for its efficiency and performance in embedded systems. One of the instructions available in the A64 instruction set is the STUR (Store Register Unscaled) instruction, which is used to store a…

APB Slave Selection Mechanism and Address Decoding in Single-Master Systems In an Advanced Peripheral Bus (APB) system with a single master and multiple slaves, the master communicates with one slave at a time. The selection of the slave is determined by the PSEL (Peripheral Select) signal, which is generated based on address decoding. The PSEL…

Cortex-R52+ Undefined Exception Triggered Post-Debug Exception The Cortex-R52+ processor is a high-performance, real-time capable core designed for safety-critical applications. It is common to encounter complex exception handling scenarios in such systems, especially when debugging is involved. In this case, the processor enters an undefined exception immediately after a debug exception. The undefined exception is triggered…

Understanding Secure and Non-Secure CONTROL Register Banked Fields in Cortex-M33 The ARM Cortex-M33 processor, which incorporates TrustZone-M technology, introduces a dual-world execution environment: Secure and Non-Secure. This separation is critical for implementing robust security architectures in embedded systems. The CONTROL register in the Cortex-M33 is one of the key registers that is banked between these…

APB3 Master and APB4/APB5 Slave Interoperability Challenges The Advanced Peripheral Bus (APB) is a key component of the ARM Advanced Microcontroller Bus Architecture (AMBA) family, designed for low-power, low-complexity peripheral interfacing. A common question arises when designing systems with APB: Can an APB3 master interface communicate effectively with an APB4 or APB5 slave? The short…

AXI4 Initiator 32-bit to APB 8-bit Target Data Transfer Challenges When designing an AXI4 to APB bridge, one of the most intricate challenges arises when dealing with data width mismatches between the AXI4 initiator and the APB target. In this scenario, the AXI4 initiator has a 32-bit data width, while the APB target operates with…

ARM Cortex-R52+ Data Abort Triggered by CPSR Write Operation The Cortex-R52+ processor is a high-performance, real-time capable core designed for safety-critical applications. It is common to encounter complex hardware-software interaction issues when working with such architectures, especially when dealing with low-level register manipulations. One such issue arises when executing the MSR CPSR_cx, #0x1F instruction, which…

ARM Cortex-A725 CASAL Instruction Fault in EL1 with MMU Enabled The issue revolves around a data abort exception (0x96000035) triggered during the execution of the CASAL (Compare and Swap Atomic Local) instruction on an ARM Cortex-A725 processor. The exception occurs in EL1 (Exception Level 1) with the MMU (Memory Management Unit) enabled, and the fault…