ARM Cortex-A53 Cores Crashing During 64-bit to 32-bit Mode Transition The issue at hand involves ARM Cortex-A53 cores 1, 2, and 3 crashing when transitioning from a power-on reset state to an execution state during a boot process that switches from 64-bit mode to 32-bit mode. The system initially runs a Built-In Test (BIT) in…
Cortex-R52+ PMU Event Count Discrepancy in Instruction Execution Measurement The Cortex-R52+ processor, like many ARM cores, provides Performance Monitoring Unit (PMU) capabilities to measure various runtime metrics, including the number of architecturally executed instructions. However, users often encounter discrepancies between the expected number of instructions and the counts reported by the PMU. This issue is…
Cortex-R52 Exception Prioritization Mechanism in AArch32 State The Cortex-R52 processor, based on the Armv8-R architecture, implements a well-defined exception prioritization mechanism to handle concurrent exceptions. This mechanism is critical for ensuring deterministic behavior in real-time systems where multiple exceptions, such as IRQs and aborts, may occur simultaneously or in close temporal proximity. The prioritization rules…
Secure World Non-Preemptive Nature and TrustZone Execution Model The ARM TrustZone architecture provides a hardware-based security foundation by partitioning the system into two distinct worlds: the Secure World and the Non-Secure World. The Secure World is designed to handle sensitive operations, such as cryptographic functions, secure boot, and trusted execution environments (TEEs), while the Non-Secure…
ARM CHI ReadShared with Exclusive Access and ReadUnique: Key Differences and Use Cases The ARM Coherent Hub Interface (CHI) specification defines a set of protocols and transactions for managing coherence and data transfers in multi-core systems. Among these transactions, ReadShared with Exclusive Access and ReadUnique are two critical operations that serve distinct purposes in managing…
AXI4 Protocol Write Interleaving Removal and Its Impact on Bus Throughput The AXI4 protocol, a cornerstone of modern ARM-based systems, explicitly removed support for write interleaving, a feature present in its predecessor, AXI3. Write interleaving allowed multiple write transactions from different masters to be interleaved at the data phase, enabling higher bus utilization in scenarios…
APU Core Crashes During 32-bit Mode Boot Process The issue involves an ARM Processing Unit (APU) with four cores (Core 0 to Core 3) executing a Built-In Test (BIT) in 64-bit mode during the Secondary Stage Boot Loader (SSBL) phase. Upon completion of the BIT, cores 1 to 3 are placed into a power-on reset…
ARM Cortex-A53 Dual-Core Synchronization Exceptions with Shared Page Tables In a dual-core ARM Cortex-A53 system, sharing page tables between cores is a common practice to simplify memory management and reduce overhead. However, this approach can lead to synchronization exceptions if the implementation is not carefully handled. This post delves into the root causes of such…
Cortex-A35 Feature Configuration and ATF Initialization Challenges The ARM Cortex-A35 is a highly efficient processor designed for power-sensitive applications, offering a balance between performance and energy efficiency. However, its flexibility in feature configuration can sometimes lead to unexpected behavior during system initialization, particularly when working with the ARM Trusted Firmware (ATF). The ATF is responsible…
Ethos-U55 MAC and Elementwise Engine Concurrency Challenges The Ethos-U55 Neural Processing Unit (NPU) is a highly optimized accelerator designed for machine learning workloads, featuring specialized engines such as the Multiply-Accumulate (MAC) Engine and the Elementwise Engine. These engines are designed to handle specific types of operations efficiently. However, a critical question arises regarding their ability…