Arm

Implementing an ARM Cortex-M0 processor on an FPGA can be an excellent way to prototype and test an embedded system design before committing to an ASIC or production FPGA. The Cortex-M0 DesignStart model provides a basic Cortex-M0 core in synthesizable RTL that can be targeted to many different FPGA devices. This article will walk through…

The Cortex-M0, Cortex-M3, and Cortex-M4 ARM processors all support both the original Thumb instruction set as well as the newer Thumb-2 instruction set. The key difference is that Thumb-2 builds upon and extends the 16-bit Thumb instruction set with 32-bit instructions to provide additional functionality while maintaining backwards compatibility with existing Thumb code. Overview of…

The main difference between Thumb-16 and Thumb-2 instruction sets is that Thumb-2 has a 32-bit instruction set architecture while Thumb-16 has a 16-bit instruction set architecture. Thumb-2 provides significant performance and code density improvements over Thumb-16. Overview of Thumb-16 Thumb-16 is a 16-bit compressed instruction set that was introduced in ARMv4 architecture in the late…

The Cortex-M processors from ARM only support the Thumb-16 instruction set. By default, the GCC compiler will generate a mix of 32-bit Thumb-2 and 16-bit Thumb instructions when compiling code for Cortex-M. However, it is possible to force GCC to emit only 16-bit Thumb instructions using compiler flags. Why limit code to Thumb-16 on Cortex-M?…

Hard faults in embedded systems running ARM Cortex processors are often caused by bugs in vendor SDKs and device drivers. Vendors provide SDKs to help developers interface with their hardware, but these SDKs can contain bugs that lead to hard faults. Similarly, vendor-supplied device drivers meant to simplify hardware integration may also harbor defects triggering…

The Cortex-M series of ARM processors are extremely popular in embedded systems due to their low cost, low power consumption, and excellent performance. All Cortex-M variants have built-in fault handling capabilities, with the HardFault exception being the catch-all fault handler for undefined faults not handled by other fault exceptions. While the HardFault mechanism is consistent…

A Hard Fault on an ARM Cortex chip refers to an unrecoverable exception that occurs when the processor detects an error condition that it cannot handle gracefully. Hard Faults result in a complete halt of normal program execution, requiring a reset or power cycle to recover. Understanding the timing, randomness, and root causes of Hard…

Hard faults on Cortex-M0/M0+ microcontrollers are often caused by software bugs, improperly configured hardware, or faulty external devices. While hard faults can seem cryptic at first, there are some common root causes to look for when debugging these issues. Software Bugs Many hard faults originate from bugs in the software code running on the MCU….

When a Cortex-M0 processor encounters a fault or exception, it pushes information onto the stack to create a stack frame. This stack frame contains key processor registers that help identify the cause of the fault. The HardFault exception is the catch-all fault handler on Cortex-M0 devices, so understanding its stack frame is crucial for debugging…

The NVIC_SystemReset() function can be used to trigger a soft reset in Cortex-M0 based microcontrollers. This function is part of the Nested Vectored Interrupt Controller (NVIC) peripheral found in ARM Cortex-M0 chips. Calling NVIC_SystemReset() will restart the microcontroller and reset most peripherals and registers to their power-on default states, while keeping power and clock configurations…